公开(公告)号：EP1668856B1

公开(公告)日：2012-02-08

申请号：EP04786458.2

申请日：2004-08-04

Applicant: STMicroelectronics, Inc

Inventor： NORSWORTHY, Steven, R. ,  REDGRAVE, Jason, Rupert

IPC: H03M3/00 ,  H04L25/49

CPC classification number: H03M3/392 ,  H03M3/394 ,  H03M3/424 ,  H03M3/448 ,  H03M3/454 ,  H03M3/498

Abstract: A noise-shaping coder with variable or reconfigurable characteristics is disclosed. In one exemplary embodiment, an improved apparatus for signal modulation is disclosed. The apparatus (see figure 1) generally comprises a noise-shaping coder having programmable coefficients, (see figure 1, CSEL), programmable coder order (see figure 1, MSEL), programmable oversampling frequency (see figure 1, CKEN), and/or programmable dither (see figure 1, D). In a second exemplary embodiment, an improved method for implementing noise shaping coding is disclosed. The apparatus generally compromises a means for switching from one order coder to another order coder, as well as switching oversampling frequency.

公开(公告)号：EP1668856A4

公开(公告)日：2007-08-15

申请号：EP04786458

申请日：2004-08-04

Applicant: ST MICROELECTRONICS INC

Inventor： NORSWORTHY STEVEN R ,  REDGRAVE JASON RUPERT

IPC: H03M3/00 ,  H03M20060101 ,  H03M3/02 ,  H04B14/06 ,  H04L25/49

CPC classification number: H03M3/392 ,  H03M3/394 ,  H03M3/424 ,  H03M3/448 ,  H03M3/454 ,  H03M3/498

Abstract: A noise-shaping coder with variable or reconfigurable characteristics is disclosed. In one exemplary embodiment, an improved apparatus for signal modulation is disclosed. The apparatus generally comprises a noise-shaping coder having programmable coefficients, programmable coder order, programmable oversampling frequency, and/or programmable dither. In a second exemplary embodiment, an improved method for implementing noise shaping coding is disclosed. The apparatus generally comprises a means for switching from one order coder to another order coder, as well as switching oversampling frequency.

公开(公告)号：EP1384327A4

公开(公告)日：2005-12-07

申请号：EP02728988

申请日：2002-04-25

Applicant: CIRRUS LOGIC INC

Inventor： TUCKER JOHN CHRISTOPHER

IPC: H03M3/02 ,  H03M3/04 ,  H03M3/00 ,  H03M1/00

CPC classification number: H03M3/32 ,  H03M3/424 ,  H03M3/448 ,  H03M3/452 ,  H03M3/454

Abstract: A method and system are disclosed for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital ("A/D) converter. A first, upstream integrator is operated with one power supply, and the other downstream integrator(s) is/are operated with at least another power supply. The modulator has amplifiers with coefficient gains having values that are determined and set so that voltage levels for the at least another integrator are maintained within operating and output limits. An integrating coefficient gain k1 for the first integrator is set to have a sufficiently large value so that an integrating capacitor can be made small for the one integrator. Another integrating coefficient gain k2 for a second integrator is set to have a sufficiently small value so that an output voltage from the first integrator is sufficiently attenuated to a voltage value within an operating range of the second integrator.

公开(公告)号：EP1263144B1

公开(公告)日：2005-03-09

申请号：EP02253249.3

申请日：2002-05-09

Applicant: Pioneer Corporation

Inventor： Yamamoto, Yuji, c/o Pioneer Corporation

IPC: H03M3/02

CPC classification number: H03M3/448 ,  H03M3/406 ,  H03M3/454

公开(公告)号：EP1980021A1

公开(公告)日：2008-10-15

申请号：EP07700660.9

申请日：2007-01-22

Applicant: NXP B.V.

Inventor： LE GUILLOU, Yann

IPC: H03M3/00

CPC classification number: H03M3/386 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

Abstract: A continuous-time sigma-delta analog-to-digital converter (CV) comprises i) a signal path (SP) comprising at least one combiner (Cl) for combining analog signals to convert with feedback analog signals, at least two integrators (Hl, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) comprising at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (Cl). Each integrator (Hl, H5) comprises variable capacitance means arranged to be set in chosen states define by the values of a digital word, to present chosen capacitances. The converter (CV) also comprises a self-calibration control means (CCM) arranged a) to generate a digital word with a chosen first value, b) to estimate an in-band noise IBN(n) from the filtered digital signals and to compare this IBN(n) to the preceding IBN(n-l), c) to modify the digital word value to decrease the capacitance of each integrator from a chosen decrement when IBN(n) is smaller than IBN(n-l), d) to iterate steps b) and c) till IBN(n) be greater than IBN(n-l), and to choose as calibration digital word value the value corresponding to IBN(n- 1) to set the calibration state of the variable capacitance means.

公开(公告)号：EP1668856A2

公开(公告)日：2006-06-14

申请号：EP04786458.2

申请日：2004-08-04

Applicant: STMicroelectronics, Inc

Inventor： NORSWORTHY, Steven, R. ,  REDGRAVE, Jason, Rupert

IPC: H04L25/49

CPC classification number: H03M3/392 ,  H03M3/394 ,  H03M3/424 ,  H03M3/448 ,  H03M3/454 ,  H03M3/498

Abstract: A noise-shaping coder with variable or reconfigurable characteristics is disclosed. In one exemplary embodiment, an improved apparatus for signal modulation is disclosed. The apparatus (see figure 1) generally comprises a noise-shaping coder having programmable coefficients, (see figure 1, CSEL), programmable coder order (see figure 1, MSEL), programmable oversampling frequency (see figure 1, CKEN), and/or programmable dither (see figure 1, D). In a second exemplary embodiment, an improved method for implementing noise shaping coding is disclosed. The apparatus generally compromises a means for switching from one order coder to another order coder, as well as switching oversampling frequency.

公开(公告)号：EP1382124A1

公开(公告)日：2004-01-21

申请号：EP02724409.4

申请日：2002-04-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： ORSIER, Elisabeth ,  BELLEVILLE, Marc ,  CONDEMINE, Cyril

IPC: H03M3/02

CPC classification number: H03M3/404 ,  H03M3/43 ,  H03M3/448

Abstract: The invention concerns a sigma-delta modulator comprising at least a resonator (110a, 110b), a converter (120) for converting an analog signal from the resonator into a digital signal with temporal information, and a feedback loop connecting an output of the converter to an excitation input of the resonator. The invention is characterised in that at least one resonator of the modulator is a resonator selected among the group comprising mechanical, acoustic, electromechanical, electrostatic, optical and chemical resonators. The invention is applicable to analog-to-digital conversion, detection and generation of signals.

公开(公告)号：EP0512687B1

公开(公告)日：1996-11-06

申请号：EP92303093.6

申请日：1992-04-08

Applicant: NOKIA MOBILE PHONES LTD. ,  FINCITEC OY

Inventor： Karema, Teppo ,  Tenhunen, Hannu ,  Ritoniemi, Tapani

IPC: H03M3/02

CPC classification number: H03M3/366 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

公开(公告)号：EP2443527B1

公开(公告)日：2013-12-25

申请号：EP10725056.5

申请日：2010-06-18

Applicant: ST-Ericsson SA

Inventor： PUTTER, Bas

IPC: G06G7/18 ,  H03M3/00 ,  G05B11/40 ,  H03K7/06 ,  H03L7/24

CPC classification number: H03L7/24 ,  G06G7/18 ,  H03K7/06 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

Abstract: An integrator (100) comprises an amplification and phase shifting element (170) with a feedback path (130) forming a loop and comprising a capacitive element (140). An input signal is summed into the loop, and the loop is arranged to oscillate at an oscillation frequency higher than the frequencies of interest in the input signal. The loop includes a filter (160) for attenuating the oscillation signal to ensure that the amplification and phase shifting element (170) can provide amplification for the input signal. The input signal is integrated and the integrated signal perturbs the zero crossings of the oscillation signal.

公开(公告)号：EP2482463A1

公开(公告)日：2012-08-01

申请号：EP12151715.5

申请日：2012-01-19

Applicant: Sony Corporation

Inventor： Niwa, Atsumi ,  Ueno, Yosuke

IPC: H03M3/00

CPC classification number: H03M3/424 ,  H03M3/448 ,  H03M3/452 ,  H03M3/454

Abstract: A ΔΣ modulator includes: a plurality of integrators cascaded to an input of an analog signal; a quantizer for quantizing an output signal of the integrator at a last stage and outputting a resultant digital signal; a DA converter for feedback for converting the digital signal obtained by the quantizer into an analog signal and supplying the analog signal to an input side of at least the integrator at a first stage; and an adder, arranged at an input stage side of the integrator at the last stage, for adding an output of the integrator at a preceding stage of the integrator at the last stage to at least one path signal supplied from at least another path via a first resistor having at least a first coefficient. The integrator at the last stage includes an operational amplifier, an integration capacitor, and a second resistor having a second coefficient.

Abstract translation: “£调制器包括：级联到模拟信号的输入的多个积分器; 量化器，用于在最后阶段量化积分器的输出信号，并输出所得数字信号; 用于将由量化器获得的数字信号转换为模拟信号的反馈的DA转换器，并且在第一级将模拟信号提供给至少积分器的输入端; 以及加法器，布置在最后级的积分器的输入级侧，用于将最后级的积分器的前级的积分器的输出与从至少另一路径经由至少一个路径信号提供的至少一个路径信号相加 第一电阻器具有至少第一系数。 最后阶段的积分器包括运算放大器，积分电容器和具有第二系数的第二电阻器。