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1.发明公开CALIBRATION OF TIME CONSTANTS IN A CONTINUOUS-TIME DELTA-SIGMA CONVERTER 审中-公开时间在恒定ZEITKONTINUERLICHENΔ-Σ转换器校准
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公开(公告)号：EP2319182A2
公开(公告)日：2011-05-11
申请号：EP09786730.3
申请日：2009-07-28
申请人： NXP B.V.
IPC分类号： H03M3/02
摘要： A method is disclosed of compensating the output of an ADC for non- linearity in the response of the ADC. The methodcomprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.
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3.发明授权A HYBRID TUNING CIRCUIT FOR CONTINUOUS-TIME SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER 有权混合调谐时间连续Σ-Δ模拟/数字转换
公开(公告)号：EP1766782B1
公开(公告)日：2008-11-19
申请号：EP05737428.2
申请日：2005-04-14
申请人： Analog Devices, Inc.
发明人： NGUYEN, Khiem , ADAMS, Robert, W.
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03J1/0091 , H03J2200/10 , H03M3/458
摘要： A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.
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4.发明公开
公开(公告)号：EP2760137A3
公开(公告)日：2015-03-11
申请号：EP14150668.3
申请日：2014-01-09
发明人： Wang, Peijun , Jones, Robert S.
IPC分类号： H03M3/00
摘要： A sigma delta modulator (100) includes a first circuit (102, 104, 106, 108, 110, 112, 114, 116, 118) that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer (120) that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit (128, 130, 132, 134, 136, 138, 140, 144, 146) that receives the intermediate signal and provides a second quantizer signal and a second quantizer (142) that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit (204, 208) having a first reference and a negative of the first reference, a first comparator (206) having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator (210) having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer.
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5.发明授权CONTINUOUS-TIME SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER WITH CAPACITOR AND/OR RESISTANCE DIGITAL SELF-CALIBRATION MEANS FOR RC SPREAD COMPENSATION 有权具有自校准电容器和/或电阻钢筋混凝土SPREAD补偿时间连续Σ-Δ模数转换器
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公开(公告)号：EP1627266A1
公开(公告)日：2006-02-22
申请号：EP03734192.2
申请日：2003-05-27
发明人： BRADY, Philomena Cleopha , LO, Haw-Jing , SERRANO, Guillermo, Jose , ADIL, Farhan , KUCIC, Matthew, Raymond , HASLER, Paul, Edward , ANDERSON, David, V. , PEREIRA, Angelo, W.
IPC分类号： G05F1/10
CPC分类号： G11C7/14 , G11C27/005 , H03M1/1057 , H03M1/36 , H03M1/74 , H03M3/386 , H03M3/45 , H03M3/454
摘要： Systems and methods are discussed for using a floating-gate MOSFET (520) as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source (705), while a second example of a programmable reference circuit is a programmable reference current source (805). The programmable voltage reference source (705) and/or the reference current source (805) may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits (900), and converter circuits. Comparator circuits and currentmirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analogto-digital converters (700, 175) and digital-toanalog converters (800, 100).
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7.发明授权
公开(公告)号：EP2342828B1
公开(公告)日：2017-03-01
申请号：EP09775123.4
申请日：2009-10-29
申请人： THALES
发明人： HODE, Jean-Michel , KAMOUN, Leila
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8.发明公开CALIBRATION OF TIME CONSTANTS IN A CONTINUOUS-TIME DELTA-SIGMA CONVERTER 审中-公开时间在恒定ZEITKONTINUERLICHENΔ-Σ转换器校准
公开(公告)号：EP2659591A1
公开(公告)日：2013-11-06
申请号：EP11852259.8
申请日：2011-10-28
IPC分类号： H03M1/10
摘要： A circuit for calibrating selective coefficients of a delta-sigma modulator is provided. The circuit includes a calibration logic module that is coupled to one of a plurality of stages of the delta-sigma modulator. The calibration logic module measures the oscillating frequency of a respective stage and compares it to a reference frequency. The calibration logic adjusts a selective circuit component associated with the respective stage so that the reference frequency and the oscillating frequency match.
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9.发明公开
公开(公告)号：EP2342828A1
公开(公告)日：2011-07-13
申请号：EP09775123.4
申请日：2009-10-29
申请人： THALES
发明人： HODE, Jean-Michel , KAMOUN, Leila
摘要： The invention relates to a method for improving the resolution and the correction of distortions in a sigma-delta modulator, wherein the modulator (200) converts an analog input signal e(t) into a secondary output digital signal s(t) sampled at a frequency fθ and encoded over NB bits, a second main output digital signal s’(t) represented over NMSB bits being also available at the output. At least three forms of processing are sequentially applied to the two outputs, the first form of processing (201) comprising a demodulation by a frequency f
0 and an N-factor decimation (202, 203) in an independent manner, the second form of processing (204) comprising an improvement of the resolution and the third form of processing (208) comprising a correction of the distortions, the three forms of processing being carried out after decimation. The invention also relates to a sigma-delta modulator implementing the method of the invention.摘要翻译： “（在用于提高分辨率和用于校正失真为Σ-Δ调制器的方法，调制器转换为输入信号模拟成在频率fe采样和编码上NB个比特，第二主输出数字信号s次级输出数字信号 吨）被表示上因此是可在输出NMSB比特。 至少三个处理被连续地施加到所述输出端，一第一处理通过频率f 0和的因子N在独立的方式抽取进行解调，用于执行的分辨率的改进和执行第三处理第二处理的 失真的校正。 这3个处理的被抽取后进行。 Σ-Δ调制器实现该方法。
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10.发明公开CONTINUOUS-TIME SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER WITH CAPACITOR AND/OR RESISTANCE DIGITAL SELF-CALIBRATION MEANS FOR RC SPREAD COMPENSATION 有权具有自校准电容器和/或电阻钢筋混凝土SPREAD补偿时间连续Σ-Δ模数转换器
公开(公告)号：EP1980021A1
公开(公告)日：2008-10-15
申请号：EP07700660.9
申请日：2007-01-22
申请人： NXP B.V.
发明人： LE GUILLOU, Yann
IPC分类号： H03M3/00
摘要： A continuous-time sigma-delta analog-to-digital converter (CV) comprises i) a signal path (SP) comprising at least one combiner (Cl) for combining analog signals to convert with feedback analog signals, at least two integrators (Hl, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) comprising at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (Cl). Each integrator (Hl, H5) comprises variable capacitance means arranged to be set in chosen states define by the values of a digital word, to present chosen capacitances. The converter (CV) also comprises a self-calibration control means (CCM) arranged a) to generate a digital word with a chosen first value, b) to estimate an in-band noise IBN(n) from the filtered digital signals and to compare this IBN(n) to the preceding IBN(n-l), c) to modify the digital word value to decrease the capacitance of each integrator from a chosen decrement when IBN(n) is smaller than IBN(n-l), d) to iterate steps b) and c) till IBN(n) be greater than IBN(n-l), and to choose as calibration digital word value the value corresponding to IBN(n- 1) to set the calibration state of the variable capacitance means.
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