公开(公告)号：EP0920750B1

公开(公告)日：2006-06-21

申请号：EP97925456.2

申请日：1997-05-05

Applicant: Telogy Networks Inc.

Inventor： BETTS, William, Lewis ,  SOUDERS, Keith, Alan

IPC: H04B15/00 ,  H04L7/00 ,  H04J3/12 ,  H04L1/16

CPC classification number: H04B14/048 ,  H04J3/125 ,  H04L25/4927

Abstract: A cooperative feedback system (210) is provided for a compensation system associated with a transmitter or codec, for enabling the compensation system to improve the accuracy of digital signals transmitted to a digital network (113). The cooperative feedback system is particularly suited for providing feedback to a compensation system (130) for correction distortion resulting from rob bits signaling (RBS), digital loss, or other types of digital signal degradation. The cooperative feedback system includes a compensation selector (204) in a transmitter (181) that combines compensations with frames of digital data by way of an addition mechanism to produce modified digital data frames. A receiver (214) is configured to receive the modified digital data frames (118b) from the digital network (113), to determine if accuracy of each of the modified digital data frames has increased based upon a corresponding compensation, and to communicate one or more quality feedback signals (118a) to the transmitter (181) via the digital network (113). The transmitter (181) receives the quality feedback signal(s) and selects and implements the compensation that yields a highest accuracy based upon the quality feedback signal(s).

公开(公告)号：EP0972352A4

公开(公告)日：2005-11-16

申请号：EP98906350

申请日：1998-02-12

Applicant: PCTEL INC

Inventor： GOLDSTEIN YURI ,  OKUNEV YURI

IPC: H03M7/00 ,  H04B14/02 ,  H04B14/04 ,  H04L25/49 ,  H04L27/00 ,  H04L27/02 ,  H04L27/34 ,  H04B1/38 ,  H03K9/00 ,  H04J3/06 ,  H04L23/02 ,  H04L27/04 ,  H04L27/36

CPC classification number: H04L27/3411 ,  H04B14/023 ,  H04B14/048 ,  H04L25/4927

Abstract: A pulse amplitude modulated (PAM) mapper (36) includes a constellation matrix memory (40) string indicating of a plurality of different constellations. The constellations are used individually or together to support a plurality of different modem data rates. The mapper (36) also includes a logic block (60), a constellation controller (65), a PAM code generation block (68), and an output register (75). The logic block receives incoming bits and groups the bits as a function of the desired or agreed upon bit rate as indicated by the constellation controller (65), and provides a plurality of each group of bits to the PAM code generation block (68), and one or more sign bits to the output register (75).

公开(公告)号：EP1157475A4

公开(公告)日：2004-12-15

申请号：EP00903326

申请日：2000-01-18

Applicant: SILICON LAB INC

Inventor： OKUNEV YURI ,  DRUCKER VITALY ,  WANG QIN ,  GOLDSTEIN YURI

IPC: H03M7/50 ,  H04B14/04 ,  H04J3/12 ,  H04L25/49 ,  H04B1/38 ,  H04L23/00 ,  H04L23/02 ,  H04L27/04 ,  H04L27/10 ,  H04L27/20 ,  H04L27/36

CPC classification number: H04J3/125 ,  H04B14/048 ,  H04L25/4927

Abstract: A method in a modem having a frame having a plurality of slots, for determining whether incoming DIL sequence information contains A-law or mu-law is provided. From the DIL sequence information, an ordered table of levels for each slot is generated. The levels of all non-robbed-bit slots are averaged, and average levels are subjected to an A-law/mu-law separation function. The separation function F1(n1,n2)=sum from i=n1 to i=n2 {L(i) - 2* [L(i-16]} effectively compares values of a first plurality of levels L(i) to twice the values of a second plurality of levels sixteen levels removed from the first plurality of levels (420). The sum is compared to a threshold (430), as the sum will be small for A-law values and large for mu-law values.

Abstract translation: 一种调制解调器中的方法，该调制解调器具有一个具有多个时隙的帧，用于确定输入的DIL序列信息是否包含A律或mu律。 从DIL序列信息中，生成每个时隙的有序表级。 平均所有非抢位时隙的电平，平均电平受到A律/ mu律分离功能的影响。 从i = n1到i = n2 {L（i）-2 * [L（i-16）}的分离函数F1（n1，n2）= sum将第一多个电平L（i） 从第一多个水平（420）中去除第二多个水平的第二多个水平的值，该总和与阈值（430）进行比较，因为对于A律值，和的总和将是小的并且对于mu律值是大的 。

公开(公告)号：EP1176743B1

公开(公告)日：2004-04-21

申请号：EP01126329.0

申请日：1995-05-03

Applicant: SONY CORPORATION

Inventor： Heddle, Robert

IPC: H04B14/04

CPC classification number: H04B14/048

公开(公告)号：EP1314158A1

公开(公告)日：2003-05-28

申请号：EP01960668.0

申请日：2001-08-15

Applicant: Koninklijke Philips Electronics N.V.

Inventor： AARTS, Ronaldus, M.

IPC: G11B20/10 ,  H04B14/04 ,  H04N7/26 ,  H03M7/30

CPC classification number: G11B20/10527 ,  H04B14/048

Abstract: Method and signal processing apparatus for reducing the number of bits of a digital input signal (Mi) comprising the steps of adding a pseudo-random noise signal (Na) to the digital input signal (Mi) to obtain an intermediate signal (Di), the pseudo-random noise signal (Na) being defined by noise parameters (Np), and quantising the intermediate signal (Di) having a word length of n bits to a reduced word length signal (Me) having a word length of m bits, n being larger than or equal to m. The method further comprises the step of quantising the intermediate signal (Di) comprises a first transfer function which is non-linear, the first transfer function being defined by non-linear device parameters (NLDp). Also, the present invention relates to a method and signal decoding apparatus for recovering an output signal (Mo) from a reduced word length signal (Me) provided by the method according to the invention.

公开(公告)号：EP1049304A1

公开(公告)日：2000-11-02

申请号：EP99973368.6

申请日：1999-12-02

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Sugino, Yukimasa, Mitsubishi Denki K. K. ,  Suzuki, Shigeaki, Mitsubishi Denki K. K. ,  Horie, Nobuyoshi, Mitsubishi Denki K. K.

IPC: H04L29/02 ,  H04B14/04 ,  H04M3/26 ,  H04J3/14

CPC classification number: H04L1/24 ,  H04B14/048 ,  H04L43/50 ,  H04M3/00 ,  H04M3/244 ,  H04Q11/04 ,  H04Q2213/13034 ,  H04Q2213/1316 ,  H04Q2213/13166 ,  H04Q2213/13213 ,  H04Q2213/13216 ,  H04Q2213/1331 ,  H04Q2213/1332 ,  H04Q2213/13322

Abstract: When there is an error in setting of a companding law of an encoder or a decoder, there is a problem of an error in judgment although it should be originally judged that the continuity of the testing channel does not exist.
Therefore, a channel check test system includes a transmitting side DCME for inserting a nonlinear quantized input test pattern into a channel to be tested, and a receiving side DCME. The receiving side DCME includes an adder for adding an offset value to an output value of a linear converting section, a sign extracting section for extracting a sign from an output signal of the adder, a delay unit for delaying the extracted sign, an exclusive OR arithmetic unit for performing an exclusive OR operation of the extracted sign and an output signal of the delay unit, a counter for counting the number of times of conformity in which an output value of the exclusive OR arithmetic unit is in conformity with a predetermined value, and a comparator for comparing a counted value of the counter and a threshold value and outputting judged results.
Existence or nonexistence of the continuity of the channel to be tested can be checked including an error in setting of the PCM companding law in one of the transmitting side DCME and the receiving side DCME.

Abstract translation: 当在编码器或解码器的压扩定律的设置中存在错误时，尽管最初应该判断测试通道的连续性不存在，但存在判断错误的问题。 因此，信道检查测试系统包括用于将非线性量化输入测试模式插入待测试信道的发送侧DCME和接收侧DCME。 接收侧DCME包括用于将偏移值与线性转换部分的输出值相加的加法器，用于从加法器的输出信号中提取符号的符号提取部分，用于延迟提取的符号的延迟单元，异或 用于执行所提取的符号的异或运算的运算单元和延迟单元的输出信号，用于计数异或运算单元的输出值与预定值一致的符合次数的计数器， 以及用于比较计数器的计数值和阈值并输出判定结果的比较器。 可以检查存在或不存在要测试的通道的连续性，包括在发送侧DCME和接收侧DCME之一中的PCM压扩法律的设置中的错误。

公开(公告)号：EP0573192B1

公开(公告)日：1998-07-22

申请号：EP93303999.2

申请日：1993-05-24

Applicant: CANON KABUSHIKI KAISHA

Inventor： Haba, Yoshito, c/o Canon Kabushiki Kaisha

IPC: H04B14/04 ,  H03G3/34

CPC classification number: H04B14/048 ,  H03G3/345

公开(公告)号：EP1161798A4

公开(公告)日：2004-12-15

申请号：EP00903325

申请日：2000-01-18

Applicant: SILICON LAB INC

Inventor： OKUNEV YURI ,  DRUCKER VITALY ,  WANG QIN ,  GOLDSTEIN YURI

IPC: H03M7/50 ,  H04B14/04 ,  H04J3/12 ,  H04L25/49 ,  H04B1/38 ,  H04L23/00 ,  H04L23/02 ,  H04L27/04 ,  H04L27/10 ,  H04L27/20 ,  H04L27/36

CPC classification number: H04B14/048 ,  H04J3/125 ,  H04L25/4927

Abstract: Methods are provided for generating at least one translation table for a modem having a frame having a plurality of slots. DIL sequence information from another is used to generate ordered table of levels (15), and distances (20) between adjacent levels of the ordered table (15) found for each slot. The distances (20) are used to distinguish between slots subject to robbed bit signaling (RBS) and slots not subject to RBS (25), and the ordered tables (15) are used to make a determination as to whether the DIL sequence information is A-law or mu -law information. Scaling factors are generated from the A-law/ mu -law determination as well as from a PAD estimation, and the scaling factors (80) are utilized in generating translation tables (100a, 100b). A PAD estimation function is utilized in finding the PAD estimation.

公开(公告)号：EP1472693A1

公开(公告)日：2004-11-03

申请号：EP02790650.2

申请日：2002-12-23

Applicant: Koninklijke Philips Electronics N.V.

Inventor： GIGI, Ercan, F.

IPC: G11B20/10 ,  H04B14/04 ,  G10L21/02 ,  H03M1/08

CPC classification number: G10L21/0208 ,  H03M1/0854 ,  H04B14/048

Abstract: A method and unit for substracting quantization noise from a pulse code modulated PCM signal being segmented into frames. For achieving this it is proposed to first calculate for each frame of the PCM signal a quantization noise level Bq according to an equation having parameters including n which indicates a specific sample of the PCM signal, S* min [n] which represents the minimum quantization noise level for a specific sample value s*[n] of the PCM signal, S* max [n] which represents the maximum quantization noise level for the specific sample value s*[n] of the PCM signal, w[n] which represents a window-function and W which represents the number of samples per window. Subsequently, the quantization noise as represented by the quantization noise level Bq has to be substracted from the PCM signal, preferably with the help of a suitable background noise substracting system. B q = ∑ n = 0 W - 1 ⁢ { ( s min * ⁡ [ n ] - s max * ⁡ [ n ] ) . w ⁡ [ n ] } 2 12 ( I )

公开(公告)号：EP0920762A4

公开(公告)日：2003-05-21

申请号：EP97931428

申请日：1997-06-25

Applicant: TELOGY NETWORKS INC

Inventor： BETTS WILLIAM LEWIS ,  SOUDERS KEITH ALAN

IPC: H03M13/00 ,  H04B14/04 ,  H04J3/12 ,  H04L12/00 ,  H04L25/49 ,  H04M11/06

CPC classification number: H04B14/048 ,  H04J3/125

Abstract: A compensation system (figure 2A) for improving the accuracy of digital signals that are communicated through a digital network (113, figure 1) by reducing loss from attenuation quantization (DAQ) and rob bit signaling (RBS). The combined DAQ/RBS compensation system can be employed within the transmitting modem (101) connected to the digital network. A first adjustment mechanism combines a DAQ compensation quantity with each segment of the digital data. Next, the word is communicated to a linear-mu-linear converter (201), which is configured to simulate a digital transmission by mu-low encoding each digital data word into a code word and then subsequently mu-low decoding each code word back into linear digital data word. The linear-mu-linear converter includes an RBS compensation system (129) that causes an RBS compensation quantity to be mathematically combined with each segment to be tainted by RBS. A second adjustment mechanism combines the reciprocal of the DAQ compensation quantity with the linear digital data from the linear-mu-linear converter. Finally, the linear digital data word is passed from the linear-mu-linear converter to a linear-mu-converter (208) for conversion into a mu-law code word and transmission to the network.