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    METHOD AND APPARATUS FOR BYTE-BY-BYTE MULTIPLEXING OF DATA OVER PARALLEL COMMUNICATION LINKS
    4.
    发明公开
    METHOD AND APPARATUS FOR BYTE-BY-BYTE MULTIPLEXING OF DATA OVER PARALLEL COMMUNICATION LINKS 有权
    对于字节的方法和装置的字节数据复用到并行新闻链接

    公开(公告)号：EP1114534A4

    公开(公告)日：2007-05-23

    申请号：EP99907130

    申请日：1999-02-18

    Applicant: GENUITY INC ,  GTE SERVICE CORP

    Inventor： PARTRIDGE CRAIG ,  MILLIKEN WALTER C

    IPC: H04J14/02 ,  H04L25/14 ,  H04J3/00 ,  H04Q3/64

    CPC classification number: H04L25/14 ,  H04J14/02 ,  H04Q2213/13093 ,  H04Q2213/13106 ,  H04Q2213/13174 ,  H04Q2213/13204 ,  H04Q2213/13216 ,  H04Q2213/1329 ,  H04Q2213/13292 ,  H04Q2213/13295 ,  H04Q2213/13322 ,  H04Q2213/13367 ,  H04Q2213/13386 ,  H04Q2213/13389

    Abstract: A communication technique for transmitting packet data over parallel communication sublinks (202, 302) coupled to a processor unit (110) is provided. Initially, a method receives a packet of data from a first communication link which is coupled to a set of sublinks (116). The method distributes packets over each of the sublinks (116) utilizing a unique byte-by-byte (BBB) striping technique. Logically, the data bytes associated with each sublink (116) are collected into a slice of data and each set of slices are given a unique predetermined label. Each slice is then synchronously transmitted at the aggregate bandwidth of each sublink (116) in parallel across each corresponding sublink (116) to a receiver (120). A receiver (120) receives the slices of data from the set of sublinks (116) and aggregates the bandwidth of these two or more communication sublinks (116) into a single communication link. Unless there are errors, a packet is transmitted in order using multiple slices. The system recreates the original packet of data from sets of slices having the same unique label. Specifically, the system uses the byte-by-byte striping technique to extract the appropriate bytes of information from each slice received over the parallel sublinks (116) based upon a predetermined sublink sequence corresponding to the labels. This technique is advantageous in that it provides an optimal balance between preserving packet order and conserving network resources.

    Switch matrix among tributaries of a telecommunication network and managing method thereof
    9.
    发明公开
    Switch matrix among tributaries of a telecommunication network and managing method thereof 审中-公开
    一个电信网络的辅助信道和管理方法为此之间的切换矩阵

    公开(公告)号：EP1610585A2

    公开(公告)日：2005-12-28

    申请号：EP05020886.7

    申请日：1999-06-18

    Applicant: ALCATEL

    Inventor： Colizzi, Ernesto ,  Lovadina, Marco

    IPC: H04Q11/04 ,  H04Q11/06

    CPC classification number: H04Q11/0478 ,  H04J2203/001 ,  H04J2203/0012 ,  H04J2203/0021 ,  H04Q11/06 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/1334 ,  H04Q2213/13367

    Abstract: A switch matrix among tributaries of a telecommunication network operating on flows of data which are arranged according to SDH protocol, said switch matrix comprising a set of parallel branches, each of said branches comprising at least a space stage able to select and pack from the input data flow a subset of data to be exchanged, a second time stage able to store the data subset to be exchanged and comprising a random access memory device associated with a write memory and a read memory, said write memory and read memory being driven by a microprocessor and a master counter. The invention is characterized in that the read memory and write memory of each random access memory device are updated in association with a spare read memory which is common to read memories on all branches in parallel and with a spare write memory which is common to write memories on all branches in parallel, respectively.

    Abstract translation: 其上布置雅丁到SDH协议的数据流操作的电信网络的支流之间的开关矩阵，所述开关矩阵，包括一组平行的分支，每个所述分支包括至少能够选择和从输入包的空间阶段 数据流要被交换的数据的一个子集，能够存储数据子集的第二时间阶段进行交换，并包括与写存储器和读存储器，所述写存储器相关联的随机存取存储器设备和读存储器由一个被驱动 微处理器和主计数器。 本发明是在做读内存，写每个随机存取存储设备关联的更新与备用读取内存中的所有这是共同的所有分支上读记忆并行并用写内存中的所有保存这是常见的写存储器的存储特点 上分别并行的所有分支。

    Verfahren und Kompensationsmodul zur Phasenkompensation von Taktsignalen
    10.
    发明公开
    Verfahren und Kompensationsmodul zur Phasenkompensation von Taktsignalen 有权
    对于时钟信号的相位补偿方法和补偿模块

    公开(公告)号：EP1223698A3

    公开(公告)日：2005-12-21

    申请号：EP01440417.2

    申请日：2001-12-10

    Applicant: ALCATEL

    Inventor： Wolf, Dr., Michael Joachim ,  Höhn, Jürgen ,  Beisel, Werner

    IPC: H04J3/06 ,  H04L7/00 ,  H04Q11/04

    CPC classification number: H04J3/0688 ,  H04J2203/0003 ,  H04Q2213/13214 ,  H04Q2213/1331 ,  H04Q2213/13322 ,  H04Q2213/1336

    Abstract: Die vorliegende Erfindung betrifft ein Verfahren sowie ein Kompensationsmodul (MOD1) zur Phasenkompensation zwischen einem ersten Taktsignal (TS1) und einem zweiten Taktsignal (TS2), die dem Kompensationsmodul (MOD1, MOD2) übermittelt werden, das insbesondere ein Kompensationsmodul in einem Telekommunikationsnetz oder in einem Netzknoten eines Telekommunikationsnetzes ist.
    Dabei wird vorgeschlagen, dass das Kompensationsmodul (MOD1, MOD2) das mindestens eine erste Taktsignal (TS1) um eine vorbestimmte erste Verzögerungsdauer (VZ1) zu einem verzögerten ersten Taktsignal (TS1d) verzögert, dass das Kompensationsmodul (MOD1) das zweite Taktsignal (TS2) um eine vorbestimmte zweite Verzögerungsdauer (VZ2) zu einem verzögerten zweiten Taktsignal (TS2d) verzögert, und dass das Kompensationsmodul (MOD1) die zweite Verzögerungsdauer (VZ2) derart modifiziert, dass das verzögerte zweite Taktsignal (TS2d) an die Phase des verzögerten ersten Taktsignals (TS1d) angepasst ist.

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