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    Clock and carrier recovery in a QAM demodulator
    4.
    发明公开
    Clock and carrier recovery in a QAM demodulator 有权
    在Einem QAM解调器中的Rückgewinnungvon Takt undTräger

    公开(公告)号：EP1146709A2

    公开(公告)日：2001-10-17

    申请号：EP01303010.1

    申请日：2001-03-29

    申请人： Mitel Semiconductor Limited

    发明人： Arambepola, Bernard

    IPC分类号： H04L27/38 ,  H04L7/02

    CPC分类号： H04L7/0004 ,  H04L7/0029 ,  H04L27/2272 ,  H04L27/3818 ,  H04L2025/03745 ,  H04L2027/003 ,  H04L2027/0036 ,  H04L2027/0038 ,  H04L2027/0067 ,  H04L2027/0073 ,  H04L2027/0077

    摘要： A QAM demodulator comprises a timing synchroniser 7 whose output is supplied via an adaptive equaliser 8 to a carrier synchroniser 9, all of which are controlled by a controller 6. The timing synchroniser 7 resamples the incoming signal in the digital domain with a sampling period which, during an acquisition mode, sweeps between limit values at different rates. The controller 6 begins an acquisition cycle at the highest rate and monotonically lowers the sweep rate until timing lock is achieved. The sampling rate is then fixed at the correct value. Similarly, the controller 6 sweeps the local oscillator of a phase locked loop in the carrier synchroniser 9 initially at a highest rate and at progressively lower rates until the carrier synchroniser 9 locks to the phase of the incoming signal.

    摘要翻译： QAM解调器包括定时同步器7，定时同步器7的输出经由自适应均衡器8提供给载波同步器9，所有这些均由控制器6控制。定时同步器7以数字域中的输入信号取样，取样周期为 在采集模式下，以不同的速率扫描极限值之间。 控制器6以最高速率开始采集周期，并且单调降低扫描速率，直到达到定时锁定。 然后将采样率固定为正确的值。 类似地，控制器6最初以最高速率和逐渐降低的速率扫描载波同步器9中的锁相环的本地振荡器，直到载波同步器9锁定到输入信号的相位。