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公开(公告)号：EP2515467B1
公开(公告)日：2016-02-10
申请号：EP11163565.2
申请日：2011-04-21
申请人： NXP B.V.
CPC分类号： H04L7/0334 , H04L7/046 , H04L27/22 , H04L2007/047
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公开(公告)号：EP2940916A1
公开(公告)日：2015-11-04
申请号：EP14176362.3
申请日：2014-07-09
申请人： NXP B.V.
IPC分类号： H04L7/033 , H04L27/227
CPC分类号： H04L7/0276 , H04L7/0012 , H04L7/0332 , H04L7/0334
摘要： A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.
摘要翻译： 一种符号时钟恢复电路，包括ADC，可控逆变器和定时检测器。 定时检测器输入端子被配置为从ADC输出端子接收ADC输出信号; 定时检测器输出端被配置为提供数字输出信号; 并且第一定时检测器反馈端子被配置为向逆变器控制端子提供第一反馈信号。 定时检测器被配置为确定与接收的ADC输出信号相关联的误差信号，并且根据误差信号设置第一反馈信号。
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公开(公告)号：EP2573716A2
公开(公告)日：2013-03-27
申请号：EP12184989.7
申请日：2012-09-19
申请人： NXP B.V.
IPC分类号： G06K19/073
CPC分类号： G06K19/07372
摘要： Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.
摘要翻译： 各种实施例涉及一种用于安全装置的防篡改电路，包括：信号延迟检测器; 时钟延迟检测器; 时钟占空比检测器; 以及保护单元，其从所述信号延迟检测器，时钟延迟检测器和所述时钟占空比检测器接收错误指示，其中所述保护单元在接收到所述错误指示时指示篡改安全装置。
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公开(公告)号：EP3525343A1
公开(公告)日：2019-08-14
申请号：EP19153906.3
申请日：2019-01-28
申请人： NXP B.V.
摘要： Aspects are directed to an amplifier circuit including a signal processing circuit and a calibration circuit. In certain specific embodiments, the signal processing circuit includes a signal combiner and a closed-loop feedback path, and the signal processing circuit is designed to provide a loop transfer function for a derived signal partly representing contributions from an audio input signal, a control or pilot signal having a target frequency range, and a calibration signal. The signal combiner is designed to combine aspects of the control or pilot signal and aspects of the audio input signal, and the calibration circuit is designed to adjust an effective gain of the derived signal in response to whether a unity-gain frequency of a signal in the closed-loop feedback path, as provided via the loop transfer function, is higher or lower than the target frequency range. Consistent therewith and in yet more specific embodiments, such an amplifier circuit can define the target frequency range relative to the transfer function and an associated unity-gain frequency.
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公开(公告)号：EP3079321B1
公开(公告)日：2019-01-30
申请号：EP15162828.6
申请日：2015-04-08
申请人： NXP B.V.
发明人： Li, Juhui , Al-kadi, Ghiath , Ciacci, Massimo
IPC分类号： H04L27/233 , H04B5/00 , H04L27/22
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公开(公告)号：EP2753038B1
公开(公告)日：2017-07-12
申请号：EP13199880.9
申请日：2013-12-31
申请人： NXP B.V.
CPC分类号： H04B1/16 , H04B1/0003 , H04B5/0081 , H04L25/0266 , H04L25/03 , H04L25/06
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8.发明公开MEMORY MISALIGNMENT CORRECTION FOR VERY HIGH BIT RATE NEAR FIELD COMMUNICATION 审中-公开SPEICHERFEHLAUSRICHTUNGSKORREKTUR
公开(公告)号：EP3079321A1
公开(公告)日：2016-10-12
申请号：EP15162828.6
申请日：2015-04-08
申请人： NXP B.V.
发明人： Li, Juhui , Al-kadi, Ghiath , Ciacci, Massimo
IPC分类号： H04L27/233 , H04B5/00 , H04L27/22
CPC分类号： H04L7/033 , H04L1/0079 , H04L7/0016 , H04L27/2331
摘要： A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.
摘要翻译： 公开了一种用于相移键控接收机中的存储器未对准的系统和模块及其校正方法。 实施例包括具有：模拟前端，用于接收具有前导码部分的解调信号，并用于产生包括接收到的前导码部分的数字寄存器输入信号; 有限状态机，用于基于所接收的前同步码部分选择解调信号的存储器地址; 前导码存储器，用于存储包含在解调信号内的所有可能的前导码，并用于提供对应于所选择的存储器地址的所选择的前同步码存储器输出; 以及存储器对准模块，被配置为比较所述前导码部分的符号的相位信息和所选择的前导码存储器输出的符号的前导码相位信息。 该系统检查寄存器输入信号的前导码部分与所选择的前同步码存储器输出对齐，并在必要时进行校正。
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公开(公告)号：EP2693634A1
公开(公告)日：2014-02-05
申请号：EP13174363.5
申请日：2013-06-28
申请人： NXP B.V.
CPC分类号： H03C5/00 , H03F3/2173 , H03F3/24 , H04L25/0272
摘要： Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.
摘要翻译： 预期具有两个产生具有引入的谐波的差分输出信号的D类开关放大器的射频（RF）发射机电路中的谐波的可配置抑制。 选择的谐波用于确定持续时间。 谐波抑制电路修改使用振幅分量和相位分量编码的射频极调制数据信号。 修改响应于确定的持续时间。 开关功率放大器放大经修改的极坐标数据信号以产生放大信号。 放大的信号包括三个信号电平，高信号电平，中间信号电平和低信号电平。 高信号电平和低信号电平之间的转换时序表示相位分量，并且转换包括持续时间的中间信号电平，由此抑制所选择的谐波。
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公开(公告)号：EP2515467A1
公开(公告)日：2012-10-24
申请号：EP11163565.2
申请日：2011-04-21
申请人： NXP B.V.
CPC分类号： H04L7/0334 , H04L7/046 , H04L27/22 , H04L2007/047
摘要： A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter (101) comprising a first input for receiving a coherent-detected baseband analog signal (104) derived from a carrier signal, a second input for receiving an adapted symbol clock signal (106), and an output for outputting a digital signal (107) comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit (102) comprising a first input for receiving a symbol clock signal (105) derived from the carrier signal, and a timing detector (103), comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal (108) comprising information about an optimum sample phase to the phase shifting unit. The timing detector is adapted for detecting at least one zero crossing between the at least two symbols of the preamble of the frame of the digital signal, for determining a phase being associated with the zero crossing, and for calculating an optimum phase for sampling the coherent-detected baseband analog signal based on the calculated phase being associated with the zero crossing. The phase shifting unit comprises a second input for receiving from the timing detector the optimum phase for sampling the coherent-detected baseband analog signal, and is adapted for shifting the phase of the symbol clock signal according to the received optimum phase to generate an adapted symbol clock signal and for providing the adapted symbol clock signal to the analog-to-digital converter.
摘要翻译： 为使用相干解调的数据通信系统提供符号时钟恢复电路。 符号时钟恢复电路包括模数转换器（101），包括用于接收从载波信号导出的相干检测的基带模拟信号（104）的第一输入端，用于接收适配符号时钟信号（106 ）和用于输出数字信号（107）的输出，包括具有至少两个符号的具有前同步码的帧的数字信号（107）。 符号时钟恢复电路还包括相移单元（102），包括用于接收从载波信号导出的符号时钟信号（105）的第一输入端和定时检测器（103），包括用于接收数字信号的第一输入端 以及用于向相移单元提供包括关于最佳采样相位的信息的信号（108）的输出端。 定时检测器适于检测数字信号的帧的前导码的至少两个符号之间的至少一个零交叉，用于确定与过零点相关联的相位，并且用于计算用于采样相干的最佳相位 基于计算出的与过零点相关联的相位的检测到的基带模拟信号。 相移单元包括第二输入，用于从定时检测器接收用于对相干检测的基带模拟信号进行采样的最佳相位，并且适于根据所接收的最佳相位移位符号时钟信号的相位，以产生适配符号 时钟信号，并用于将适配符号时钟信号提供给模数转换器。
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