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22 条记录 (耗时 0.008 秒)

    Digital signal processor
    2.
    发明公开
    Digital signal processor 失效
    数字信号处理器

    公开(公告)号：EP0551931A2

    公开(公告)日：1993-07-21

    申请号：EP93104195.8

    申请日：1988-06-01

    申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

    发明人： Murakami, Tokumichi, c/o Mitsubishi Denki K. K. ,  Kamizawa, Koh, c/o Mitsubishi Denki K. K. ,  Katoh, Yoshiaki, c/o Mitsubishi Denki K. K. ,  Ohira, Hideo, c/o Mitsubishi Denki K. K. ,  Kameyama, Masatoshi, c/o Mitsubishi Denki K. K. ,  Kinjo, Naoto, c/o Mitsubishi Denki K. K.

    IPC分类号： G06F15/78 ,  G06F9/26 ,  G06F9/36

    CPC分类号： G06F7/575 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/345 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/786 ,  G06F2207/3884

    摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

    摘要翻译： 一种简单电路结构的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

    Vorrichtung zur Adressumwandlung in einer Datenverarbeitungsanlage
    5.
    发明公开
    Vorrichtung zur Adressumwandlung in einer Datenverarbeitungsanlage 失效
    装置用于在数据处理系统中的地址转换。

    公开(公告)号：EP0010195A1

    公开(公告)日：1980-04-30

    申请号：EP79103611.4

    申请日：1979-09-24

    申请人： International Business Machines Corporation

    发明人： Mitchell, Glen Robert ,  Houdek, Merle Edward

    IPC分类号： G06F9/36 ,  G06F13/00 ,  G11C8/00

    CPC分类号： G06F17/30949 ,  G06F12/1027

    摘要： Zur Umwandlung virtueller Adressen in Hauptspeicheradressen in einem Computer wird eine Hash-Tabelle (20) benützt. Ein Hash-Generator (100) erzeugt eine gleichmässige Verteilung der Tabelleneinträge trotz ungleichmässiger Verteilung der virtuellen Adressen in einem System mit im Hinblick auf die Hauptspeichergrösse variabler Hash-Tabellengrösse. Ein Bitfeld innerhalb der virtuellen Adresse, das die Seitenidentifikationsbits (PID) umfasst, wird umgekehrt und mit zwei Bitgruppen eines Feldes in der virtuellen Adresse, das die Objektidentifikation umfasst, ausgerichtet. Die drei Bitgruppen werden einer exklusiv-ODER-Schaltung zugeführt. Die Ausrichtung der drei Bitgruppen und die Grösse der Hash-Tabelleneintragsadressen, die erzeugt werden, hängen von der Grösse der Hash-Tabelle ab.

    摘要翻译： 将虚拟地址转换成主存储地址在使用哈希表（20）的计算机。 哈希发生器（100）产生的表中的条目的尽管虚拟地址的不均匀分布的均匀分布在系统中，以对主存储器大小可变的哈希表的大小。 虚拟地址内的位字段，其包括所述Seitenidentifikationsbits（PID）被对准反转，并且与该虚拟地址，其包括对象ID的字段中的两个比特组。 三组位被提供给异或电路。 三个位组的方位和将要产生的哈希表入口地址的大小依赖于哈希表的大小。

    DATAFLOW PROCESSING ELEMENT, MULTIPROCESSOR, AND PROCESSES
    9.
    发明公开
    DATAFLOW PROCESSING ELEMENT, MULTIPROCESSOR, AND PROCESSES 失效
    数据流处理元件，多处理器和处理器

    公开(公告)号：EP0315647A4

    公开(公告)日：1991-01-30

    申请号：EP87905809

    申请日：1987-07-13

    申请人： DENNIS, JACK B.

    发明人： DENNIS, JACK B.

    IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F3/00 ,  G06F9/30 ,  G06F9/36 ,  G06F9/38 ,  G06F9/40 ,  G06F13/00

    CPC分类号： G06F9/4436

    摘要： This invention provides a novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of dataflow processing elements communicate externally by means of input/output circuitry, and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions. In accordance with the present invention, these instructions include associations of execution components and enable components identified by instruction indices.

    METHOD AND APPARATUS FOR DATA COMPRESSION.
    10.
    发明公开
    METHOD AND APPARATUS FOR DATA COMPRESSION. 失效
    方法和装置进行压缩数据。

    公开(公告)号：EP0160672A4

    公开(公告)日：1986-05-12

    申请号：EP84903871

    申请日：1984-10-17

    申请人： TEXT SCIENCES CORP

    发明人： TAGUE LOUIE DON ,  COBB ALLEN T

    IPC分类号： G06F5/00 ,  G06F17/22 ,  H03M7/30 ,  H03M7/42 ,  H04L23/00 ,  G06F9/36 ,  G06F15/38

    CPC分类号： G06F17/22 ,  H03M7/42

    摘要： A method and apparatus for compressing alphanumeric data that is stored or transmitted in the form of digital codes. A dictionary is created which assigns each word of the alphanumeric text and the punctuation that follows it to a unique address or token of, illustratively, up to 16 bits (two bytes). Each word in the alphanumeric text is then replaced by the address that refers to that word in the dictionary. Because the dictionary can contain up to 2 = 65,536 entries, it is more than adequate for the storage of the words associated with almost any book. Because only two bytes of information are needed to address any one of these 65,000 words, replacement of each word of text with two bytes of address information reduces the average number of digits required to store the text by a factor of about three. Further reductions of 25% or more in the length of the compressed text can be achieved in most cases by representing the most frequency used words with tokens that are shorter than two bytes in length. The number of bytes required to store the dictionary can be substantially reduced by storing the words in alphabetical order and taking advantage of the redundancy in characters that results. Thus, if the second of two entries contains five letters that are the same as that of the preceding entry, this can be signified by storing one character representing the number 5 and the remaining characters not common to both entries.