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公开(公告)号：EP0168246A3
公开(公告)日：1988-04-27
申请号：EP85304920
申请日：1985-07-10
申请人： NEC CORPORATION
IPC分类号： G11C11/40 , G11C07/00 , H03K19/017 , H03K17/04 , H03K03/00 , H03K03/356
CPC分类号： H03K3/35606 , G11C11/4094 , H03K3/356095 , H03K19/01742
摘要： An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption. A first switch is provided between a refresh voltage terminal and a time circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.
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公开(公告)号：EP0162370A3
公开(公告)日：1988-02-17
申请号：EP85105583
申请日：1985-05-07
发明人： Demler, Michael John
IPC分类号： H03K03/356 , G11C07/06
CPC分类号： G01R19/0038 , G11C7/065 , H03K3/35606 , H03K3/356095 , H03K3/356156 , H03K5/249
摘要： The voltage comparator includes a first and a second voltage supply terminal, and a first and a second output node. A first current source is connected between the first supply terminal and the first output node. A first field effect transistor of one channel conductivity type is connected between the first output node and the second supply terminal. The gate of the first transistor is connected to the second output node. A second current source is connected between the first sup- plyterminal and the second output node. A second field effect transistor of the one conductivity is connected between the second output node and the second supply terminat. The gate of the second transistor is connected to the first output node. During a first period of time the first and second output nodes and the capacitances of the gates of the first and second transistors connected thereto are maintained at the potential of the second supply terminal by switches connected ther- eacross. Atthe end of the first period the switches are opened allowing the first and second output nodes to charge. Simultaneously charge proportional to a first signal voltage is supplied to the first output node and charge proportional to a second signal voltage is supplied to the second output node. The node which receives the greater charge rapidly charges toward the voltage of the first supply terminal and the node which receives the smaller charge is maintained at the potential of the second supply terminal. Thus, an indication is obtained of the greater of the two voltages.
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公开(公告)号：EP0028935A3
公开(公告)日：1982-05-12
申请号：EP80304024
申请日：1980-11-11
IPC分类号： G11C11/00 , G11C11/40 , G11C11/34 , H03K03/356
CPC分类号： G11C14/00
摘要： An NMOS non-volatile latch having N-channel drivers Q 1 and Q 2 and variable threshold N-channel FATMOS transistors O 3 and O 4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X, or X 2 ) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.
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公开(公告)号：EP0186773A3
公开(公告)日：1988-11-23
申请号：EP85114818
申请日：1985-11-22
IPC分类号： H03K03/356 , G11C07/00 , G11C11/24
CPC分类号： H03K3/356086 , G11C7/12 , G11C11/4094 , H03K3/0375
摘要： A soft error protection circuit is disclosed for a storage cell, such as a latch (6) having a first input/output node (8') and a second input/output node (8) which are respectively connected to a charging source (10), the first node (8') being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor (18) having a diffusion electrode (20) connected to the second node (8) and having a gate electrode (22), for selectively loading the second node (8) with an additional capacitance. An inverter circuit (2 4 ) has an input (26) connected to the second node (8) and an output (28) connected to the gate electrode (22) of the capacitor (18), for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node (8). The charging source (10) supplies charge to both the first node (8') and the second node (8) at least following a soft error event which has caused the first node (8') to become at least partially discharged during the read interval. In accordance with the invention, the additional capacitance applied to the second node (8) prevents the second node from recharging as fast as the first node (8') following the soft error event, by sinking a portion of the charge supplied from the charging source (10) to the second node. In this manner, the first node will resume its previously charged condition, thereby preserving the stored logic state.
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公开(公告)号：EP0153860A3
公开(公告)日：1987-09-30
申请号：EP85301311
申请日：1985-02-27
申请人： FUJITSU LIMITED
发明人： Suyama, Katsuhiko
IPC分类号： H03K19/094 , H03K03/356
CPC分类号： H03K19/0952 , H03K3/35606 , H03K19/01707
摘要： A logic circuit includes a driver transistor (Q s ) and a load transistor (Q 6 ), each a junction type or Schottky barrier type field effect transistor, and an input terminal (V IN ) connected to a gate of the driver transistor. A gate voltage generator (1) is connected to a gate of the load transistor and generates a level higher than the sum of threshold values of the load transistor and the driver transistor and lower than a low value among the first sum of a built-in voltage of the load transistor and the threshold voltage of the driver transistor and the second sum of a built-in voltage of the driver transistor and the threshold voltage of the load transistor.
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公开(公告)号：EP0196894A3
公开(公告)日：1987-09-02
申请号：EP86302332
申请日：1986-03-27
IPC分类号： H03K03/356 , G11C19/28
CPC分类号： H03K3/356104 , G11C19/28 , H03K3/3562
摘要： A CMOS D-type flip-flop circuit stage for avoiding the possibility of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.
摘要翻译： 用于避免馈通的可能性的CMOS D型触发器电路级包括具有真实时钟输出和补充时钟输出的非重叠时钟发生器部分。 触发器电路包括由第一传输门，第一再生晶体管和第一反相器门形成的主部分。 触发器电路还包括由第二传输门，第二再生晶体管和第二反相器门形成的从部分。 时钟发生器提供了一个两相非重叠时钟，用于对主控部分和从属部分进行时钟控制，以防止数据输入无意中穿过连续的阶段。
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公开(公告)号：EP0135136A3
公开(公告)日：1987-05-06
申请号：EP84109633
申请日：1984-08-13
IPC分类号： H03K03/356
CPC分类号： H03K3/356017
摘要： Integrierte RS-Flipflop-Schaltung mit zwei kreuzgekop pelten Invertern, die jeweils aus einem Feldeffekttransistor (T1, T2) und einem in Serie geschalteten Widerstandsele ment (R1, R2) bestehen. Jeder Feldeffekttransistor ist mit einem zusätzlichen Schaltelement (T3, T4) verbunden, des sen Steuereingang den R- bzw. S-Eingang darstellt. Ange strebt wird eine Realisierung der Flipflopschaltung auf einer möglichst kleinen Halbleiterfläche. Das wird erreicht durch eine Ausbildung der zusätzlichen Schaltelemente (T3, T4) als Heiße-Elektronen-Transistoren, von denen jeder mit einem der Feldeffekttransistoren (T1, T2) zu einem gemeinsamen Bauelement (5, 6) zusammengefaßt wird, das zwei Transi storfunktionen übernimmt, aber nur die Fläche eines Feld effekttransistors benötigt. Der Anwendungsbereich umfaßt hochintegrierte Schaltungskreise.
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公开(公告)号：EP0199287A3
公开(公告)日：1987-04-01
申请号：EP86105295
申请日：1986-04-16
发明人： Yang, Ji Leon , Zeh, Joseph P.
IPC分类号： H03K19/094 , H03K03/356
CPC分类号： H03K19/09436 , H03K3/356034
摘要： A source follower current steering logic circuit useful in, for example, fabricating digital integrated logic circuits using gallium arsenide and current mode logic switches. The circuit includes an input logic network which includes level shifting networks to generate output signals having assertion levels of different voltage levels and a reference voltage logic network having a similar level shifting network for generating reference voltages relative to the voltage levels of the assertion levels of the output signals from the input logic network. A logic tree includes current mode logic switches for receiving the output signals from the input logic network and the reference voltage generating network to perform selected logic operations the output signals. The output signals are taken from the logic tree. A top load clamps the output signals to selected voltage levels.
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公开(公告)号：EP0103236A3
公开(公告)日：1987-02-25
申请号：EP83108602
申请日：1983-08-31
发明人： Koike, Hideharu
IPC分类号： H03K19/094 , H03K03/356 , H03K03/80
CPC分类号： H03K3/354 , H03K3/356104 , H03K3/3565 , H03K19/09485
摘要： A logic circuit comprises a first and second circuit. The first circuit consists of at least one first conductivity-type MOSFET (14, 23, 33, 43) whose gate is connected to an input terminal, and which is connected at one end to an output terminal. The second circuit consists of at least one second conductivity-type MOSFET (15, 24, 34, 44) whose gate is connected to the input terminal, and which is connected at one end to the output terminal. The gate of the second conductivity-type MOSFET (15,24,34,44) is connected to the input terminal, and one end of this MOSFET is connected to the output terminal. The logical circuit further comprises a depletion-type MOSFET (13, 21, 31, 41) of the second conductivity type and a depletion-type MOSFET (16, 22, 32, 42) of the first conductivity type. The depletion-type MOSFET (13, 21, 31, 41) of the second conductivity type has a threshold voltage the absolute value of which is larger than that of the first conductivity-type MOSFET (14, 23, 33, 43), is connected between the other end of the first conductivity-type MOSFET (14, 23, 33, 43) and a first power source, and has its gate connected to the output terminal. The depletion-type MOSFET (16, 22, 32, 42) of the first conductivity type has a threshold voltage the absolute value of which is larger than that of the second conductivity-type MOSFET (15, 24, 34, 44) is connected between the other end of the second conductivity-type MOSFET (15, 24, 34, 44) and a second power source, and has its gate connected to the output terminal.
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公开(公告)号：EP0045020A3
公开(公告)日：1983-03-30
申请号：EP81105636
申请日：1981-07-17
IPC分类号： G11C11/24 , H03K03/356
CPC分类号： G11C11/4091
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