公开(公告)号：EP4406056A1

公开(公告)日：2024-07-31

申请号：EP22777928.7

申请日：2022-09-02

Applicant: QUALCOMM INCORPORATED

Inventor： WANG, Chuan ,  HEDAYATI, Maziar ,  ASURI, Bhushan Shanti ,  HASSAN, Muhammad ,  MISHRA, Chinmaya ,  DAVIERWALLA, Anosh

IPC: H01P1/18 ,  H03H7/18

CPC classification number: H01P1/18 ,  H03H7/185 ,  H04B1/40 ,  H03H7/20

公开(公告)号：EP3188428A4

公开(公告)日：2017-09-06

申请号：EP15836598

申请日：2015-08-24

Applicant: WILKERSON BENJAMIN P

Inventor： WILKERSON BENJAMIN P

IPC: H04L27/233 ,  H03H7/18 ,  H03H7/30 ,  H03H11/04 ,  H03K3/023 ,  H03K3/3565 ,  H04B1/7163 ,  H04L7/033 ,  H04L27/00 ,  H04W4/00 ,  H04W84/18

CPC classification number: H04L27/2331 ,  H04B1/71637 ,  H04B2201/71636 ,  H04L7/0278 ,  H04L27/0014 ,  H04L27/2334 ,  H04L27/2335 ,  H04L2027/0036 ,  H04W4/008

Abstract: An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. Provided is an ultra low power wideband asynchronous BPSK demodulation circuit configured by comprising: a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter of which a cutoff frequency is a carrier frequency, so as to output an analog signal delayed by a ¼ period of the carrier frequency from an upper sideband analog signal, and a lower sideband analog signal; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0°, that is, an analog pulse signal indicated according to a phase shift part of a BPSK modulation signal, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

Abstract translation: 本发明的一个实施例涉及超低功率宽带异步二进制相移键控（BPSK）解调方法及其电路配置。 提供一种超低功率宽带异步BPSK解调电路，包括：边带分割和上边带信号延迟单元，通过一阶高通滤波器和一阶低通滤波器将调制信号分成上边带和下边带， 其截止频率为载波频率，以从上边带模拟信号和下边带模拟信号输出延迟了载波频率的1/4周期的模拟信号; 数据解调单元通过迟滞电路锁存由延迟的上边带模拟信号和下边带模拟信号之间的相位差在0°排列的模拟信号之间的差异所产生的信号，即，模拟信号 根据BPSK调制信号的相移部分指示脉冲信号，以解调数字数据; 以及数据时钟恢复单元，用于通过使用通过比较器和数据信号从下边带模拟信号数字化的信号来生成数据时钟。

公开(公告)号：EP2649727A2

公开(公告)日：2013-10-16

申请号：EP11846303.3

申请日：2011-12-12

Applicant: Wispry, Inc.

Inventor： GU, Qizheng ,  DE LUIS, Javier, R. ,  MORRIS, Arthur, S. III

IPC: H03H7/01 ,  H03H7/18 ,  H03H9/66 ,  H01P1/20

CPC classification number: H03H7/0153 ,  H03H9/547 ,  H03H9/6409 ,  H03H2007/008 ,  H03H2007/013 ,  H04B1/525

Abstract: Tunable notch filters and control loop systems and methods can include a tunable notch filter providing a stop band, a sensing circuit in communication with the tunable notch filter and adapted to determine a phase change between a reference signal and a signal reflected from the tunable notch filter, and a control loop in communication with the tunable notch filter and the sensing circuit, the control loop being operable to adjust the tunable notch filter to modify the phase change.

公开(公告)号：EP0675621A3

公开(公告)日：1998-10-21

申请号：EP95104490

申请日：1995-03-27

Applicant: NEC CORP

Inventor： MINEO MASAHO

IPC: H01P3/08 ,  H03H7/18 ,  H03H7/20 ,  H04L27/20 ,  H04L27/36

CPC classification number: H04L27/2064

Abstract: The present invention has an object to provide a compact quadrature modulator manufactured at low cost in such a manner that an input level is low over a wide high frequency band, and few input signals are wrapped around an output terminal. The quadrature modulator is mainly constructed of a multi-layer substrate into which a 90-degree phase shifter is assembled, a semiconductor integrated modulator circuit into which two sets of 2-phase modulators and an output signal in-phase synthesizing circuit, and a lid. The multi-layer substrate is constructed of "n" pieces of layers in total, namely from a first substrate corresponding to an uppermost layer to an n-th substrate corresponding to a lowermost layer. The first substrate layer is a layer for assembling a semiconductor integrated circuit, or a layer for connecting a substrate with a semiconductor integrated circuit. The 90-degree phase shifter is constituted by distributed coupling circuits having wavelengths of λg/4 by both of wiring patterns formed on the substrates corresponding to an intermediate layer of the multi-layer substrate. A wiring pattern connected to a ground terminal and other circuit components are formed on the n-th substrate layer, i.e., the, lowermost layer.

Abstract translation: 本发明的目的是提供一种以低成本制造的紧凑型正交调制器，使得输入电平在宽的高频带上为低，并且很少的输入信号缠绕在输出端子上。 正交调制器主要由组装90度移相器的多层基板，两组2相调制器和输出信号同相合成电路组成的半导体集成调制电路构成，盖子 。 多层基板总共由n层构成，即从对应于最下层的最上层到第n层的第一衬底构成。 第一衬底层是用于组装半导体集成电路的层或用于将衬底与半导体集成电路连接的层。 90度移相器由形成在与多层基板的中间层相对应的基板上的布线图案的两个波长为λg / 4的分布耦合电路构成。 连接到接地端子和其他电路部件的布线图案形成在第n基片层，即最下层。

公开(公告)号：EP4277014A1

公开(公告)日：2023-11-15

申请号：EP22793626.7

申请日：2022-08-08

Applicant: FUJIKURA LTD.

Inventor： UEMICHI, Yusuke

IPC: H01P1/185 ,  H03H7/30 ,  H03H7/18

Abstract: A digital phase shifter of the present invention is a digital phase shifter in which digital phase shift circuits are cascade-connected, each of the digital phase shift circuits including a signal line, a pair of inner lines provided on both sides of the signal line, a pair of outer lines provided on outer sides of the inner lines, a first ground conductor connected to one ends of the inner lines and one ends of the outer lines, a second ground conductor connected to the other ends of the outer lines, and a pair of electronic switches provided between the other ends of the inner lines and the second ground conductor. The digital phase shift circuits include a multi-row structure constituted by a front row and a rear row, the front row and the rear row are adjacent to each other, and the ground pattern is connected to the front row at one point.

公开(公告)号：EP3664215B1

公开(公告)日：2022-09-21

申请号：EP18211012.2

申请日：2018-12-07

Inventor： Karabey, Onur Hamza ,  Gölden, Felix ,  Gäbler, Alexander

IPC: H01P1/18 ,  H01Q3/36 ,  H03H7/18

公开(公告)号：EP3264521B1

公开(公告)日：2020-01-01

申请号：EP17178343.4

申请日：2017-06-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhou, Jie ,  Qian, Huizhen ,  Luo, Xun

IPC: H01P1/18 ,  H01P5/08 ,  H01P5/12 ,  H03H7/18 ,  H01Q21/00 ,  H01Q3/34 ,  H01Q21/22

公开(公告)号：EP3097640A1

公开(公告)日：2016-11-30

申请号：EP14828621.4

申请日：2014-12-22

Applicant: Qualcomm Incorporated

Inventor： EHYAIE, Danial

IPC: H03H7/18 ,  H03H7/20 ,  H01P1/18 ,  H01Q3/38

CPC classification number: H03H7/20 ,  H01P1/184 ,  H01Q1/246 ,  H01Q3/38 ,  H03H7/185 ,  H04L25/0298

Abstract: Certain aspects of the present disclosure provide apparatus for producing an output signal that may have a phase difference with respect to an input signal. One example phase shifting circuit for producing such an output signal generally includes a transmission line having first and second points, an impedance connected with a node and with a reference voltage level, a first switch connected with the first point of the transmission line and with the node, and a second switch connected with the second point of the transmission line and with the node, wherein a first signal input to the first point of the transmission line has a phase difference with a second signal output from the second point based on one or more properties of the transmission line when the first and second switches are open.

公开(公告)号：EP2232702A1

公开(公告)日：2010-09-29

申请号：EP09702484.8

申请日：2009-01-14

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： SHIRAKAWA, Alexandre ,  DAVID, Jean-Baptiste ,  WURM, Patrick

IPC: H03H9/58 ,  H03H7/18

CPC classification number: H03H9/584 ,  H03H9/02228 ,  H03H9/589 ,  H03H9/60

Abstract: A power amplifier filter for radio-frequency signals having an outphasing type architecture comprising a first stage (2) capable of generating, from an input signal s(t), two signals S1(t), S2(t) having an identical amplitude but phase shifted relative to each other, a second amplifier stage (3) for said signals S1(t), S2(t), and a third recombining stage (4) capable of summing the two signals s'1(t), s'2(t) obtained from second stage (3), characterized in that recombining stage (4) includes an assembly of acoustic wave resonators coupled to each other, some of these resonators referred to as 'input resonators' being connected to the outputs of second stage (4) and others of these resonators referred to as 'output resonators' being connected to the output terminals of the filter.

公开(公告)号：EP1363398A4

公开(公告)日：2008-03-12

申请号：EP03701021

申请日：2003-01-07

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： MIYAGUCHI KENICHI ,  HIEDA MORISHIGE ,  KASAHARA MICHIAKI ,  TAKAGI TADASHI ,  HATAMOTO MIKIO

IPC: H01P1/185 ,  H03H7/18 ,  H03H7/20 ,  H03H11/20

CPC classification number: H03H7/18 ,  H01P1/185 ,  H03H7/20 ,  H03H11/20

Abstract: A small-sized, wideband phase shifting circuit and phase shifter comprising a capacitor; a switching element exhibiting a capacitance during OFF state; and a series circuit constituted by an inductor series connected to the switching element, the series circuit being connected in parallel with the capacitor; wherein an end of the capacitor and an end of the series circuit are connected to an input/output terminal of high frequency signals, while the other ends are connected to the ground.