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    Stochastic A/D converter and method for using the same
    3.
    发明公开
    Stochastic A/D converter and method for using the same 有权
    Stochastischer Analog-Digital-Wandler und Verwendungsverfahrendafür

    公开(公告)号：EP2546992A1

    公开(公告)日：2013-01-16

    申请号：EP11173743.3

    申请日：2011-07-13

    申请人： IMEC

    发明人： Verbruggen, Bob ,  Craninckx, Jan

    IPC分类号： H03M1/04 ,  H03M1/20 ,  H03M1/16 ,  H03M1/44 ,  H03M1/46

    CPC分类号： H03M1/201 ,  H03M1/04 ,  H03M1/164 ,  H03M1/44 ,  H03M1/46

    摘要： The present invention is related to an analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal (1) and for outputting a digital representation (6) of said analog input signal (1). The A/D converter circuit comprises:
    - a first converter stage (2) configured for receiving the analog input signal (1) and for generating a first set (3) of conversion bits, a first completion signal (7) and a residual analog output signal (4) representing the difference between the analog input signal and a signal represented by said first set of conversion bits,
    - a second converter stage (5) comprising
    o a clock generation circuit (8) arranged for receiving the first completion signal and for generating a clock signal,
    o a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions,
    o a digital processing stage (9) configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits,

    - means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.

    摘要翻译： 本发明涉及一种被配置用于接收模拟输入信号（1）并用于输出所述模拟输入信号（1）的数字表示（6）的模拟（A / D）转换器电路。 A / D转换器电路包括： - 第一转换器级（2），被配置为接收模拟输入信号（1）并产生第一组（3）转换位，第一完成信号（7）和残余模拟 输出信号（4），其表示模拟输入信号和由所述第一组转换位表示的信号之间的差; - 第二转换器级（5），包括被设置用于接收第一完成信号的时钟产生电路（8） 生成时钟信号，多个比较器被配置为用于接收残余模拟输出信号和公共参考电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定，数字处理阶段 （9），被配置为用于接收所述多个比较器判定并用于生成第二组转换位; - 用于生成所述转换位的数字表示的装置 模拟输入信号通过组合第一和第二组转换位。

    ACCURACY ENHANCEMENT TECHNIQUES FOR ADCS
    5.
    发明公开
    ACCURACY ENHANCEMENT TECHNIQUES FOR ADCS 审中-公开

    公开(公告)号：EP3565122A1

    公开(公告)日：2019-11-06

    申请号：EP19181554.7

    申请日：2014-09-25

    申请人： Analog Devices, Inc.

    发明人： SHEN, Junhua ,  KAPUSTA, Ronald A.

    IPC分类号： H03M1/06 ,  H03M1/04 ,  H03M1/46

    摘要： Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.

    PSEUDORANDOM DITHER FOR FREQUENCY SYNTHETIS NOISE
    9.
    发明公开
    PSEUDORANDOM DITHER FOR FREQUENCY SYNTHETIS NOISE 失效
    PSEUDORANDOM几次频率合成噪声

    公开(公告)号：EP0390868A4

    公开(公告)日：1992-03-11

    申请号：EP89901402

    申请日：1988-12-08

    申请人： QUALCOMM, INC.

    发明人： KERR, RICHARD, J. ,  WEAVER, LINDSAY, A.

    IPC分类号： H03M1/04 ,  G06F1/03 ,  G06F3/05 ,  G06J1/00 ,  H03B28/00 ,  H03M1/08 ,  H03M1/10 ,  H03M1/66 ,  G06F7/38

    CPC分类号： G06J1/00 ,  G06F1/0328 ,  G06F2101/04 ,  G06F2211/902

    摘要： A method and apparatus for reducing spurious output noise in digital frequency synthesizers that employ a sine amplitude converter (16) connected to a Digital-to-Analog converter (18) for generating an analog waveform from sine amplitude data. The method comprises the steps of adding random or pseudorandom numbers which are scaled to have a predetermined magnitude to the sine amplitude data and transferring a resulting addend to the Digital-to-Analog converter (18). The apparatus comprises a summation circuit (22) connected between an output of the sine function converter (18) and an input of the digital-to-analog converter and connected to a random or pseudorandom number generator (24) at a second input. A scale element (26) adjusts the pseudorandom number magnitude to provide numbers having values in the range +/- 1/2 times a minimum quantization step or at least significant bit of the Digital-to-Analog converter (18) resolution where n is greater than or equal to 1.