Abstract:
A receiver for deciding which signal points were sent from a transmitter based on corresponding noise affected signals received via a distorting channel, the noise affected signals carrying information about a particular sequence of encoding states occupied in a succession of time intervals by a finite state process having a finite number of possible encoding states, the receiver including modifying circuitry for generating a plurality of different modified versions of each received signal, and a decoder for deciding which signal points were sent based on estimating a particular sequence of decoder states by storing a number of path histories of previous signal points and using the modified versions to , extend the path histories, the different modified versions of each received signal numbering fewer than the number of stored path histories. In other aspects, the constellation of signal points is partitioned into decision subsets, each possible transitions from a possible decoder state are associated with a decision subset, based on the signal points in the path histories, and each of the modified versions is associated with one of the decision subsets; there are fewer modified versions than the number of decoder states; and the decoder states number fewer than the number of decoder states in an optimum trellis decoder.
Abstract:
Embodiments of apparatus are described for transmitting a stream of information bits by sending corresponding signals over a channel in a plurality of signalling slots. A family of multi-dimensional convolutionally coded modulation systems achieves enlarged minimum distance between possible sequences of signal points, reduced number of error events with the minimum distance, acceptable peak-to-average power ratio, reduced number of signal points in each constituent two-dimensional constellation, immunity to rapid carrier phase changes, and reduced complexity, resulting in a reduced error probability when maximum likelihood decoding is used. These advantages are achieved by the construction and by the partitioning into subsets of the multi- dimensional constellation, by the design of convolutional codes using those multi-dimensional subsets, by using a bit converter and a block encoder to convert a multi-dimensional constellation mapping into multiple two-dimensional constellation mappings, and by a simplified decoding technique.
Abstract:
A code conversion system is described for converting a stream of data between first and second data codes. The stream of data containing data packets is recognized to be subject to a data fault condition arising from the collision of data packets. The conversion system comprises means for detecting the fault condition, and means for altering the code conversion of the stream of data between the first and second codes so as to reflect the occurrence of the fault condition in the code converted stream of data.
Abstract:
An audibly distinctive test signal provided by a generator (6) is a pink noise signal at a standard level with periodic but brief interruptions (optimized for the ear's memory for level and spectral differences) acting as an identifier. The test signal is applied to a recording medium or transmission channel (14), preferably via an equalizer (16) and gain setting means (181. The test signal recovered from the recording medium or transmission channel by playback or receiving means (22) is compared and matched to a reference uninterrupted pink noise signal provided at a standard level by a generator (24). The interruptions are used to switch between the test and reference signals and to provide via equalizer (34) and speaker (28) an audible cue as to the identity of the signal heard at any moment so that a rapid confirmation and adjustment, if necessary, of recording/reproduction or transmis- sion/reception calibration can be achieved primarily by ear and, if desired, also by applying the signals to measuring instruments, such as a meter (30) and spectrum analyser (32).
Abstract:
A detector of predetermined patterns of Manchester encoded data signals (PRICHL) in which the voltage levels of the half-bit cells of "n" sequential Manchester bit cells, where "n" is an integer greater than zero, are clocked into a shift register (12-1, 12-2), the pattern of 2 "n" voltage levels of 2 "n" half-bit cells of the "n" sequential Manchester bit cells stored in the register at any given time are examined by a programmable logic array (18) which produces an output signal when the pattern of outputs of the shift register corresponds to the predetermined patterns (Fig. 1).
Abstract:
A communication system including a transceiver for transmitting and receiving a signal comprising a plurality of channels one of which consists of analogue speech signals and at least one other of which consists of data signals transmitted at intervals and interleaved with the speech signals, the data signals each comprising at least one complete cycle of a frequency or frequencies, which lie within the audio frequency spectrum wherein the significance of the data i.e. '0' or' 1', is defined in dependence upon its phase or frequency and wherein the data signal transmission rate is determined in dependence upon error rate detected in relation to the data signals received at a remotely located transceiver.
Abstract:
Eine Schaltungsanordnung (1) zur Kontrolle der Daten fernübertragung, welche zwischen einer Daten abgebenden ein und/oder empfangenden Einheit, beispielsweise einem Rechner (4) oder einem Endgerät (7), und einem mit einer Datenfernübertragungsleitung (6) verbindbaren Modem (5) angeordnet oder mit dem Modem (5) kombiniert ist, weist einen Datenpuffer, einen Programmspeicher, einen Mikro prozessor und einen Zeitgeber auf, wobei für den Anschluss der Daten abgebenden und/oder empfangenden Einheit eine serielle Standardschnittstelle (V24) und bei Verwendung ei nes gesonderten Modems (5) für den Anschluss desselben ebenfalls eine serielle Standardschnittstelle (V24) sowie zur Verbindung der seriellen Standarschnittstelle(n) mit dem Datenbus des Mikroprozessors ein Asynchron-Sender/Em pfänger vorgesehen sind. Der Mikroprozessor steuert in Ab hängigkeit vom Datenanfall eine zeichen- oder eine blocko rientierte Übertragung unter Voraussetzung jeweils eines Synchronisierbits, wobei die Adressierungen im sendersei tigen und im empfängerseitigen Datenpuffer synchron laufen und zur Angabe, wieviel einer empfangenen Meldung er kannt wurde, ein Zeichen ACK/NACK übertragen wird. Nach einer Anzahl K zu übertragender Zeichen sendet der Mikro prozessor ein Blockprüfzeichen BCC und bewirkt, falls zu sendende Zeichen im Pufferspeicher enthalten sind, die Übertragung bis zum K Zeichen sowie, falls keine richtige Meldung zuletzt empfangen wurde und das vorige Zeichen ein Blockprüfzeichen war, die Beendigung der Übertragung.
Abstract:
Error multiplication in a V.22 bis modem is avoided by using forward error correction and single symbol coding instead of differential coding. In the receiver section (25b) the error syndrome bit of the error corrector (32) is used in establishing phase and timing synchronization by causing the symbol detector (26) of the receiver (25b) to try all possible combinations of phase and timing, and to lock onto the combination which produces a minimum of error syndrome bits. The descrambler (30) receives the error-free corrected bit stream.
Abstract:
A channel quality monitoring apparatus provided in terminal equipment of a digital radio communication system comprises a syndrome generator circuit (10-13) responsive to a digital multiplexed signal of a receiving signal, a signal converter circuit (14) for converting an error-corrected digital multiplexed signal into a digital multiplexed signal with which a predetermined parity detection is possible. a parity detector circuit (15) for effecting a parity detection of the digital multiplexed signal from the signal converter circuit (14), and computing circuitry configured as an error rate detector circuit (16) responsive to outputs from the syndrome means (10-13) and the parity detector circuit (15). When occurrence of code error detected on the basis of the syndrome continues for the duration more than a predetermined time period, the computing circuitry is operative to compute an error rate of the receiving digital multiplexed signal on the basis of the syndrome. In contrast, when occurrence of code error detected continues for the duration equal to or less than the predetermined time period, the computing circuitry is operative to compute an error rate of the receiving digital multiplexed signal on the basis of the output from the parity detector circuit (15). Thus, this apparatus provides an improved detection accuracy of a channel error rate in the equipment of receiving and demodulating systems.