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1.发明公开
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2.发明公开Method of locating error sources in digital systems, and scrambler/descrambler for carrying out this method 失效在数字系统中定位错误源的方法以及执行此方法的SCRAMBLER / DESCRAMBLER
公开(公告)号：EP0094902A3
公开(公告)日：1985-11-27
申请号：EP83730049
申请日：1983-05-13
IPC分类号： H04L01/24
CPC分类号： H04L1/24
摘要： In digitalen Anlagen, zB Netzen, und Einrichtungen, zB Verstärkern, Repeatern, Koppelfeldern und dergleichen, sol len für Untersuchungen und auch zur laufenden Überwa chung Fehlerquellen begrenzter Fehlerhäufigkeit, also keine Totalausfälle, frühzeitig erkannt und geortet werden. Nach dem erfindungsgemäßen Vorschlag werden mit Hilfe von Scramblern SCi / Descramblern DSCi zunächst von diesen begrenzte Subsysteme i gebildet. Infolge unterschiedlicher Beschaltung der einzelnen Scrambler/Descrambler-Paare verwürfeln diese die digitalen Daten nach einem für das betreffende Subsystem typischen Muster. Am Ausgang des letzten Subsystems wird das ankommende Testsignal ge prüft. Als Testsignale kommen feste Muster, durch PROM- Schaltwerke bestimmte oder Pseudo-Random Datenmuster sowie insbesondere ein leerer Zeitmultiplex-Kanal in Be tracht. Treten in Subsystemen bitverfälschende Fehler auf, werden diese vom betreffenden Descrambler DSCi auf seine ihm eigentümliche Art vervielfältigt. Es entstehen also jeweils für ein Subsystem typische Abweichungsmuster. Am Empfangsort werden die Abweichungsmuster registriert, dargestellt und ausgewertet. Hierfür können entsprechend programmierte Geräte eingesetzt werden.
摘要翻译： 在数字系统中，例如网络和设施，例如放大器，中继器，交换网络等，有限误差频率的错误源（也就是说不是全部故障）应当在使用的早期被检测和定位 用于调查和连续监测。 根据本发明的提案，首先通过加扰器SCi /解扰器DSCi形成有限子系统i。 由于各个加扰器/解扰器对不同地连接，所以它们根据相关子系统典型的模式来对数字数据进行加扰。 在最后一个子系统的输出端检查输入测试信号。 要使用的测试信号是固定模式，由PROM网络或伪随机数据模式确定的数据模式，特别是空时分复用信道。 如果在子系统中出现位错误错误，则以相关的解扰器DSCi的方式将其相乘。 因此，在每种情况下都产生了子系统典型的偏差模式。 在接收位置，记录，显示和评估偏差模式。 为此目的可以使用适当编程的设备。
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公开(公告)号：EP0179465A3
公开(公告)日：1988-07-06
申请号：EP85113477
申请日：1985-10-23
申请人： NEC CORPORATION
发明人： Yoshimoto, Makoto
CPC分类号： H04L1/24
摘要： A channel quality monitoring apparatus provided in terminal equipment of a digital radio communication system comprises a syndrome generator circuit (10-13) responsive to a digital multiplexed signal of a receiving signal, a signal converter circuit (14) for converting an error-corrected digital multiplexed signal into a digital multiplexed signal with which a predetermined parity detection is possible. a parity detector circuit (15) for effecting a parity detection of the digital multiplexed signal from the signal converter circuit (14), and computing circuitry configured as an error rate detector circuit (16) responsive to outputs from the syndrome means (10-13) and the parity detector circuit (15). When occurrence of code error detected on the basis of the syndrome continues for the duration more than a predetermined time period, the computing circuitry is operative to compute an error rate of the receiving digital multiplexed signal on the basis of the syndrome. In contrast, when occurrence of code error detected continues for the duration equal to or less than the predetermined time period, the computing circuitry is operative to compute an error rate of the receiving digital multiplexed signal on the basis of the output from the parity detector circuit (15). Thus, this apparatus provides an improved detection accuracy of a channel error rate in the equipment of receiving and demodulating systems.
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公开(公告)号：EP0125805A3
公开(公告)日：1986-07-30
申请号：EP84302609
申请日：1984-04-17
申请人： NEC CORPORATION
发明人： Otani, Susumu
CPC分类号： H04L27/2275 , H04L1/241
摘要： A bit error detection circuit comprises first demodulator means supplied with a reference carrier wave for phase-demodulating an input PSK modulated carrier wave into a first demodulated signal; carrier wave recovery means for providing the reference carrier wave in response to the input PSK modulated carrier wave or the first demodulated signal; clock signal recovery means for providing a clock signal in response to the input PSK modulated carrier wave or the first demodulated signal; oscillator means; modulator means for phase-modulating the reference carrier wave with the output of the oscillator means; second demodulator means supplied with the output of the modulator means for phase-demodulating the input PSK modulated carrier wave into a second demodulated signal; first discriminator means for discriminating the first demodulated signal into a first digital signal in response to the clock signal; second discriminator means for discriminating the second demodulated signal into a second digital signal in response to the clock signal; and comparator means for comparing the first digital signal with the second digital signal to provide a bit error detection signal.
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公开(公告)号：EP0208558A3
公开(公告)日：1988-01-20
申请号：EP86305359
申请日：1986-07-11
申请人： NEC CORPORATION
发明人： Tsukakoshi, Takashi
CPC分类号： H04L25/4906 , H04L1/246
摘要： An optical repeater receives a signal A comprising a main, CMI-coded signal with superimposed sub-information signal bits which violate every nth bit of the main signal. The received signal A is processed by an opto-electronic converter 1, a circuit 2 extracting a timing signal B, a regenerating circuit 3 and a CMI decoding circuit 4 which extracts the main signal and a violation signal C representative of sub-information. A violation signal generating circuit 5 superimposes new sub-information signals DO' etc. to form a violation signal J which is imposed on the main signal by a coding circuit 6. whose output is applied to an electronic-to-optical converter 7. In the generating circuit 5 an error detecting circuit 52 produces an error pulse E for each detected error in the violation signai C. An error position varying circuit 53 varies the phase of the error pulse E in order to prevent a transmission error being erased by the superimposition of the local sub-information H. The phase-adjusted error pulses I are added in a circuit 54 to the local sub-information signal H to form the violation signal J.
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公开(公告)号：EP0112716A3
公开(公告)日：1987-06-24
申请号：EP83307793
申请日：1983-12-21
CPC分类号： H04L5/20 , H04B17/0087 , H04L1/24
摘要： A secondary data channel is described for use in a four-wire communication system in which there is continuous wire between each of two coupling transformers at a first station and each of two coupling transformers at a second station. In accordance with the invention, the transformer windings at each station that are connected to the transmission line wires are equipped with center taps G that are connected to a secondary channel data set. By these means a secondary data signal can be transmitted from one station to another by applying a signal to the center taps of the two coupling transformers at one station and receiving such signals from the center taps of the two coupling transformers at the other station.
摘要翻译： 描述了用于四线通信系统中的辅助数据信道，其中在第一站处的两个耦合变压器中的每一个和第二站处的两个耦合变压器中的每一个之间存在连续导线。 根据本发明，连接到传输线路的每个站处的变压器绕组配备有连接到次级通道数据组的中心抽头G。 通过这些意思，可以通过将信号施加到一个站处的两个耦合变压器的中心抽头并从另一个站处的两个耦合变压器的中心抽头接收这样的信号，从而将一个辅助数据信号发送到另一个站。
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公开(公告)号：EP0106985A3
公开(公告)日：1986-07-16
申请号：EP83108586
申请日：1983-08-31
CPC分类号： H04B17/408 , H04B17/401
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公开(公告)号：EP0186420A3
公开(公告)日：1988-10-05
申请号：EP85309199
申请日：1985-12-17
发明人： Bemis, Gerald L.
CPC分类号： H04L12/433
摘要： A code conversion system is described for converting a stream of data between first and second data codes. The stream of data containing data packets is recognized to be subject to a data fault condition arising from the collision of data packets. The conversion system comprises means for detecting the fault condition, and means for altering the code conversion of the stream of data between the first and second codes so as to reflect the occurrence of the fault condition in the code converted stream of data.
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公开(公告)号：EP0118763A3
公开(公告)日：1987-07-22
申请号：EP84101290
申请日：1984-02-08
申请人： HITACHI, LTD.
摘要： A method of searching fault locations which is-employed in a transmission system comprising a transmitting terminal (1) having a transmitter (2) for transmitting a digital signal; a receiving terminal (5) having a receiver (8) for receiving the digital signal; a plurality of repeaters (4, 4, ...) which are placed between the transmitting and receiving terminals, and each of which receives and amplifies the digital signal from a preceding repeater section and deliver it to a subsequent repeater section; and a plurality of transmission lines (3, 3, ...) for connecting the transmitter with the first repeater, the repeaters with each other and the final repeater with each other and the final repeater with the receiver, respectively. This method comprises the steps of coding an orginal signal to be transmitted in terms of two kinds of error detecting codes at the transmitting terminal to send out them from the transmitter; detecting an error of a received signal using one of the two kinds of error detecting codes at each repeater thereby to measure the error rate occurred at one repeater section corresponding to each repeater; recording a decoded received signal using the error detecting code employed to detect the error, and delivering it to a subsequent repeater section; and transmitting signals each of which represents the error rate at each repeater section measured at each repeater, to the transmitting terminal or receiving terminal.
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公开(公告)号：EP0114390A3
公开(公告)日：1987-05-13
申请号：EP83113038
申请日：1983-12-23
申请人： NEC CORPORATION
发明人： Murai, Masao
IPC分类号： H04L01/24
CPC分类号： G06F7/02
摘要： In a bit pattern check circuit, there are provided three memory devices and a bit pattern input is divided into portions of the number same as that of the memory devices. One portion of the divided bit pattern input is stored in the first memory device. The second and third memory devices are inputted with the other portions of the divided bit pattern and outputs of preceding memory devices respectively. The content of the third or last stage memory device is outputted through an OR gate circuit. This bit pattern check circuit has a simple construction but can accurately check a plurality of bit patterns each comprising a plurality of bits.
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