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1.发明公开
公开(公告)号：EP1804382A2
公开(公告)日：2007-07-04
申请号：EP07008257.3
申请日：2004-12-01
CPC分类号： H04B13/005
摘要： The present invention relates to an integrator comprising a first switching means, one end of which is connected to a voltage source (Vdd) outputting a predetermined voltage. Also, the integrator comprises a second switching means (SW2), which is connected at one end to the first switching means (SW1) and the other end with a negative electrode of the voltage source (Vdd). A first comparison means (211) compares a predetermined first threshold voltage (V1) and an input voltage for output of a signal to turn on the first switching means (SW1), when the input voltage is lower than the first threshold voltage (V1). A second comparison means (212), compares an input voltage and a second threshold voltage (V1), higher than the first threshold voltage (V1) for output of a signal to turn on the second switching means (SW2) when the input voltage is higher than the second threshold voltage (V2). A capacitor (213) of the integrator has one end connected to the other end of the first switching means (SW1). A signal appearing on the other end of the first switching means (SW1) is output as an output signal of the integrator. Thereby, when neither the first switching means (SW1) nor the second switching means (SW2) is turned on, no large current flows from the voltage source (Vdd) to earth ground, thereby preventing a power consumption from increasing.
摘要翻译： 本发明涉及到在积分器包括第一开关装置，所有被连接到电压源（VDD）的输出廷预定电压一端。 因此，积分器包括在一端连接到第一开关装置（SW1），其另一端与电压源（VDD）的负电极的第二开关装置（SW2），全部。 第一比较装置（211）比较的预定第一阈值电压（V1）和输入电压的一个信号的输出，以接通第一开关装置（SW1）当输入电压高于第一阈值电压低（V1） ， 第二比较装置（212）比较输入电压和第二阈值电压（V1）比的信号的输出，以接通第二开关装置（SW2）当输入电压是所述第一阈值电压（V1）高 大于第二阈值电压（V2）更高。 积分器的电容器（213）的一端连接到第一开关装置（SW1）的另一端。 出现在第一开关装置（SW1）的另一端的信号是作为对所述积分器的输出信号而输出。 由此，当既不是第一开关装置（SW1），也不是第二开关装置（SW2）被接通时，来自电压源（VDD）至大地，从而防止消耗电力的增大没有大的电流流过。
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公开(公告)号：EP0916139B1
公开(公告)日：2003-07-09
申请号：EP98905554.6
申请日：1998-03-12
发明人： HUGHES, John, Barry
CPC分类号： G06G7/12 , G11C27/028
摘要： A current memory cell comprises a fine MOS memory transistor (T1) and a coarse MOS memory transistor (T2) connected in series between two power supply rails. Such current memory cells are preferably designed so that the sum of the voltage drops across the coarse and fine memory transistors when diode connected is equal to the supply voltage. In order to achieve this while leaving flexibility in choosing the transistor saturation voltages an auxiliary power rail (Vdda) is generated using as a reference the voltage drops across two diode connected transistors (T6, T7) which conduct a current equal to the bias current in the current memory cell (3).
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3.发明公开Improved method and circuit arrangement for processing signal 失效Verfahren und Schaltungsanordnung zur Signalverarbeitung
公开(公告)号：EP0841629A3
公开(公告)日：1998-12-23
申请号：EP97660117.9
申请日：1997-11-04
发明人： Rapeli, Juha , De Albuquerque Epifânio Da Franca, José , De Almeida De Azeredo Leme, Carlos Mexia , Zuna Bello, Jo o Paulo , De Sousa Cardoso Lopes, Pedro Ant nio , Dos Santos Reis, Ricardo
IPC分类号： G06G7/184
CPC分类号： G06G7/184
摘要： The object of the invention is an improved method and arrangement for processing a signal. The invention can preferably be used for processing analog signals in embodiments wherein it is essential to achieve small energy consumption. By the term signal processing one means, in this context, for example, the summing, difference, integration and differentiation of voltage representing a signal, or charge or current equally well. In the solution according to the invention, charge transfer from signal voltage (U s ) to integrating capacitance (C o ) is exploited by means of charge transfer capacitance (C i ), an active element (T) and controllable switches (S 1 , S 3 ). The operation of the circuit according to the invention is additionally based on the fact that the charge transfer to the charge transfer capacitance (C i ) is terminated when the transistor (T) is in a current-carrying state and that current flow is ensured by means of a constant-current element set according to the invention. According to the invention, these features are combined preferably in such a way that the breaking current of charge transfer is equally great as previously said current of the constant-current element.
摘要翻译： 本发明的目的是用于处理信号的改进的方法和装置。 在实现其中必须实现小的能量消耗的实施例中，本发明可以优选地用于处理模拟信号。 在术语信号处理中，在这种情况下，例如，表示信号的电压，或电荷或电流相等的求和，差分，积分和微分是一种手段。 在根据本发明的解决方案中，通过电荷转移电容（Ci），有源元件（T）和可控开关（S1，S3）来利用从信号电压（Us）到积分电容（Co）的电荷转移。 根据本发明的电路的操作另外基于以下事实：当晶体管（T）处于载流状态时电荷转移到电荷转移电容（Ci）终止，并且电流通过装置确保 根据本发明的恒流元件组。 根据本发明，优选地将这些特征组合成电荷转移的断开电流与先前所述恒流元件的电流相同。
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公开(公告)号：EP0479374B1
公开(公告)日：1997-09-03
申请号：EP91202493.2
申请日：1991-09-26
发明人： Seevinck, Evert
IPC分类号： G06G7/184
CPC分类号： G06G7/184
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5.发明公开
公开(公告)号：EP0621550A2
公开(公告)日：1994-10-26
申请号：EP94302712.8
申请日：1994-04-15
发明人： Rapeli, Juha
IPC分类号： G06G7/184
CPC分类号： G06G7/184
摘要： The present invention relats to a method for processing a signal, and a signal processing circuit according to the method, in which circuit one or two transistors (T1, T2) switched according to the switches are used as the active member of the entire circuit, the charge passing through said transistors being controlled, in addition to the switches, by the transferrable charge itself so that on concluded transfer of charge, all current flow in the circuit stops by itself. By means of the present invention, the signal processing is, irrespective of the polarity of the signal (positive or negative) and of the threshold voltages (Uth1, Uth2) of the transistors, linear because the signal voltage (U S ) is produced, as taught by the invention, relative to a reference voltage (U Ref ) of predetermined magnitude in that a sum of the signal voltage (U S ) and said reference voltage (U Ref ) is produced and the polarity of said sum is every time the same as the polarity of the reference voltage (U Ref ), irrespective of the variation of the signal voltage (U S ), and when charge samples proportional to the signal voltage (U S ) are taken, a quantity thereof is taken which is proportional to the sum (U S + U Ref ) of the signal voltage (U S ) and the reference voltage (U Ref ), whereby the charge samples pro-portional to said sum (U S + U Ref ) are transferred to the integrating capacitance (C 0 ) included in the circuit, and thereafter, a quantity of charge samples proportional to the reference voltage (U Ref ) is added into the integrating capacitance (C 0 ) with an opposite polarity relative to the polarity of the charge samples proportional to said sum (U S + U Ref ).
摘要翻译： 本发明涉及用于处理信号的方法以及根据该方法的信号处理电路，其中根据开关切换的一个或两个晶体管（T1，T2）用作整个电路的有源部件， 除了开关之外，通过所述晶体管的电荷受到可传输电荷本身的控制，使得在完全转移电荷时，电路中的所有电流自身停止。 通过本发明，不管信号（正或负）的极性和晶体管的阈值电压（Uth1，Uth2）的极性如何，信号处理是由于产生信号电压（US）而线性的，如 通过本发明教导的相对于预定幅度的参考电压（URef），其中产生信号电压（US）和所述参考电压（URef）之和，并且所述和的极性每次与极性相同 的参考电压（URef），与信号电压（US）的变化无关，并且当采取与信号电压（US）成比例的电荷采样时，采用与总和成比例的量（US + URef ）的信号电压（US）和参考电压（URef），由此将所述总和（US + URef）的电荷采样转移到电路中包括的积分电容（C0），之后， 的电荷样本与re成正比 将谐振电压（URef）相对于与所述和（US + URef）成比例的电荷样本的极性具有相反极性而加到积分电容（C0）中。
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6.发明公开A method of and a circuit arrangement for processing sampled analogue electrical signals 失效一种用于处理采样模拟电信号的电路布置方法
公开(公告)号：EP0308008A3
公开(公告)日：1991-01-23
申请号：EP88201934.2
申请日：1988-09-07
CPC分类号： G06G7/184 , G11C27/028
摘要： A sampled analogue electrical signal in the form of sample currents is processed by combining the input sample current in one sample period with sample currents derived from input sample currents in preceding sample periods. The signal processing is performed by scaling, adding, subtracting and storing sample currents. A circuit arrangement for carrying out the signal processing may be constructed from current mirror circuits and a current memory which is capable of reproducing at its output in one sample period the current applied to its input in a previous sample period.
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7.发明公开A method of and a circuit arrangement for processing sampled analogue electrical signals 失效用于处理采样的模拟电信号的方法和电路装置。
公开(公告)号：EP0308008A2
公开(公告)日：1989-03-22
申请号：EP88201934.2
申请日：1988-09-07
CPC分类号： G06G7/184 , G11C27/028
摘要： A sampled analogue electrical signal in the form of sample currents is processed by combining the input sample current in one sample period with sample currents derived from input sample currents in preceding sample periods. The signal processing is performed by scaling, adding, subtracting and storing sample currents.
A circuit arrangement for carrying out the signal processing may be constructed from current mirror circuits and a current memory which is capable of reproducing at its output in one sample period the current applied to its input in a previous sample period.摘要翻译： 在样品的电流的形式的取样模拟电信号由输入采样电流与来自在preceding-样本周期的输入采样电流来源的样品的电流一个样本周期组合处理。 的信号处理进行放大，缩小等加，减和储存样品的电流。 用于进行信号处理的电路装置可从电流镜像电路构成，并且当前存储器中的所有其能够在其输出在一个取样周期施加的电流在先前的采样周期再现到其输入的。
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公开(公告)号：EP2418604A2
公开(公告)日：2012-02-15
申请号：EP11158450.4
申请日：2011-03-16
发明人： Liu, Tung-Jung
IPC分类号： G06G7/184
CPC分类号： G06G7/184
摘要： An integrator circuit is provided in the present invention, which utilizes a first capacitor and a first switching unit to sample an input signal and carries out distribution of charges between the first capacitor and a second capacitor. The second capacitor is larger than the first capacitor in capacitance. The integrator circuit transmits the charges stored in the second capacitor to a node of the first capacitor which is coupled to a ground previously. Accordingly, a direct current voltage level of the first capacitor may increase, facilitating an increase in a direct current voltage level at the second capacitor. Thereby, the accuracy and linearity of the integrator circuit may improve.
摘要翻译： 在本发明中提供了一种积分器电路，其利用第一电容器和第一开关单元对输入信号进行采样，并在第一电容器和第二电容器之间执行电荷分布。 第二电容器大于电容器中的第一电容器。 积分器电路将存储在第二电容器中的电荷传输到先前耦合到地的第一电容器的节点。 因此，第一电容器的直流电压电平可能增加，有助于增加第二电容器的直流电压电平。 由此，可以提高积分电路的精度和线性度。
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9.发明授权Signal processing circuit suitable for a transceiver in a communication system using the human body as a transmisssion medium 有权用于发射器/在通信系统中与人体接收机作为信号传输介质的信号处理电路
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10.发明公开
公开(公告)号：EP1851671A2
公开(公告)日：2007-11-07
申请号：EP06710743.3
申请日：2006-01-25
申请人： NXP B.V.
IPC分类号： G06G7/184
CPC分类号： G06G7/184 , H03G11/002 , H03G11/02 , H03K5/08
摘要： A voltage integrator, comprising a resistor (4) and a capacitor (5) connected in series between an input voltage (V) and ground, wherein the resistance (R) of said resistor and the capacitance (C) of said capacitor are adapted such that a voltage (Vc) across said capacitor approximates the integral of said input voltage (V). Means are provided for preventing said capacitor voltage (Vc) from falling below a lower limit, preferably zero, thereby ensuring automatic initialization of the integrator after each integration cycle.
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