公开(公告)号：EP3439044B1

公开(公告)日：2023-09-06

申请号：EP18185156.9

申请日：2018-07-24

发明人： Hürner, Andreas ,  Erlbacher, Tobias

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L27/02 ,  H01L29/808 ,  H01L29/06

公开(公告)号：EP4220729A1

公开(公告)日：2023-08-02

申请号：EP22153545.3

申请日：2022-01-26

申请人： Infineon Technologies Austria AG

发明人： Weber, Hans

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/04 ,  H01L29/808 ,  H01L29/08

摘要： A method for forming a semiconductor device and a semiconductor device are disclosed. The method includes: forming a trench structure (2) with a plurality of trenches (22) in an inner region (130) and an edge region (140) of a SiC semiconductor body (100) such that the trench structure (2) extends from a first surface (101) of the semiconductor body (100) through a second semiconductor layer (120) into a first semiconductor layer (110) and such that the trench structure (2), in the second semiconductor layer (120), into forms a plurality of mesa regions; and forming at least one transistor cell (1) at least partially in each of the mesa regions (121) in the inner region (130). Forming each transistor cell (1) includes forming at least one compensation region (17), forming the at least one compensation region (17) includes implanting dopant atoms of a second doping type via sidewalls of the trenches (22) into the mesa regions (121) in the inner region (130), and forming the at least one compensation region (17) in each of the mesa regions (121) in the inner region (121) includes at least partially covering the edge region (140) with an implantation mask (301; 401).

公开(公告)号：EP3682467B1

公开(公告)日：2022-12-28

申请号：EP18770009.1

申请日：2018-09-14

发明人： SCHÖNER, Adolf ,  RESHANOV, Sergey ,  THIERRY-JEBALI, Nicolas ,  ELAHIPANAH, Hossein

IPC分类号： H01L21/329 ,  H01L21/337 ,  H01L29/808 ,  H01L29/872 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L29/10

公开(公告)号：EP4016586A1

公开(公告)日：2022-06-22

申请号：EP21818171.7

申请日：2021-05-24

申请人： Nuvoton Technology Corporation Japan

发明人： KANDA, Yusuke ,  MIYAJIMA, Kenichi

IPC分类号： H01L21/28 ,  H01L29/41 ,  H01L29/417 ,  H01L21/336 ,  H01L29/78 ,  H01L21/337 ,  H01L29/808 ,  H01L21/338 ,  H01L29/812 ,  H01L29/778

摘要： A semiconductor device (100) includes: a channel layer (103) that is a group III nitride not containing Al; a barrier layer (104) above the channel layer (103), which is a group III nitride containing Al; a recess (106); and an ohmic electrode (108) in the recess, which is in ohmic contact with a two-dimensional electron gas layer (105). An Al composition ratio distribution of the barrier layer (104) in a first direction perpendicular to a surface of a substrate (101) has a maximum point at a first position (109). The semiconductor device (100) includes, in the first direction: a first inclined surface (110) of the barrier layer (104) which includes the first position (109) and is in contact with the ohmic electrode (108); and a second inclined surface (111) of the barrier layer (104) which intersects the first inclined surface (110) on a lower side of the first inclined surface (110), and is in contact with the ohmic electrode (108). To the surface of the substrate (101), an angle of the second inclined surface (111) is smaller than an angle of the first inclined surface (110). A position of the first intersection line (114) in the first direction is lower than the first position (109).

公开(公告)号：EP4000101A1

公开(公告)日：2022-05-25

申请号：EP20751434.0

申请日：2020-07-15

申请人： Atomera Incorporated

发明人： BURTON, Richard ,  HYTHA, Marek ,  MEARS, Robert J.

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/15 ,  H01L29/08 ,  H01L29/423 ,  H01L29/808 ,  H01L29/93

公开(公告)号：EP3961678A1

公开(公告)日：2022-03-02

申请号：EP21174891.8

申请日：2016-07-12

申请人： United Silicon Carbide Inc.

发明人： LI, Zhongda ,  BHALLA, Anup

IPC分类号： H01L21/337 ,  H01L29/808 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10

摘要： A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. The channel is doped via angled implantation, and the width of the trenches and mesas in the active cell region may optionally be varied from those in the termination region.

公开(公告)号：EP3696863B1

公开(公告)日：2021-10-13

申请号：EP19157393.0

申请日：2019-02-15

发明人： MAHMOUD, Ahmed ,  WILLMEROTH, Armin

IPC分类号： H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L21/337 ,  H01L29/36 ,  H01L29/08 ,  H01L27/06 ,  H01L29/417

公开(公告)号：EP3291284B1

公开(公告)日：2021-03-10

申请号：EP17188724.3

申请日：2017-08-31

发明人： Tokuda, Rie ,  Oda, Masaya ,  Hitora, Toshimi

IPC分类号： H01L21/36 ,  H01L29/24 ,  H01L29/04 ,  H01L29/739 ,  H01L29/778 ,  H01L29/808 ,  H01L29/872 ,  H01L33/02

公开(公告)号：EP3190608B1

公开(公告)日：2020-11-25

申请号：EP15837484.3

申请日：2015-08-28

申请人： Flosfia Inc.

发明人： Oda, Masaya ,  Takatsuka, Akio ,  Hitora, Toshimi

IPC分类号： H01L21/365 ,  H01L29/04 ,  H01L29/24 ,  H01L29/739 ,  H01L29/778 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812 ,  H01L29/872 ,  H01L33/16 ,  H01L33/26

公开(公告)号：EP3712954A1

公开(公告)日：2020-09-23

申请号：EP18878569.5

申请日：2018-11-15

申请人： Flosfia Inc.

发明人： MATSUDA Tokiyoshi ,  SUGIMOTO Masahiro ,  SHINOHE Takashi

IPC分类号： H01L29/12 ,  H01L21/28 ,  H01L21/329 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L29/41 ,  H01L29/47 ,  H01L29/739 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812 ,  H01L29/872

摘要： The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).