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公开(公告)号：EP2955847B1
公开(公告)日：2018-07-11
申请号：EP15168777.9
申请日：2015-05-21
CPC分类号： H03H7/325 , G01S13/882 , H03H11/265
摘要： Systems and methods for a variable delay line using variable capacitors in a time delay filter are provided. In at least one embodiment, a delay line is configured to apply an adjustable time delay to an electromagnetic signal travelling through the delay line. The delay line comprises a filter that includes a first variable capacitor. Further, a capacitance of the first variable capacitor is configured to adjust the delay applied to the electromagnetic signal travelling through the delay line when varied.
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公开(公告)号：EP3014768A4
公开(公告)日：2017-02-22
申请号：EP14818603
申请日：2014-06-25
申请人： ESS TECH INC
发明人： MALLINSON A MARTIN
IPC分类号： H03K5/15 , H03H11/26 , H03K5/133 , H03K5/14 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K5/133 , H03K5/14 , H03K5/15046 , H03K19/00361 , H03K19/00369 , H03K19/018521
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3.发明公开APPARATUS AND SYSTEM FOR GENERATING A SIGNAL WITH PHASE ANGLE CONFIGURATION 审中-公开VORRICHTUNG系统ZUR ERZEUGUNG EINES SIGNALS MIT PHASENWINKELKONFIGURATION
公开(公告)号：EP2795794A4
公开(公告)日：2015-10-21
申请号：EP11877725
申请日：2011-12-23
申请人： INTEL CORP
CPC分类号： H02M1/14 , G06F1/26 , H02M2003/1586 , H03H7/325 , H03H11/265 , H03K3/0315 , H03K4/06 , H03K5/133 , H03K5/134 , H03K7/08 , H03K2005/00019 , H03K2005/00195 , H03L7/00
摘要： Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.
摘要翻译： 这里描述了一种用于产生具有相位角配置的信号的装置和系统。 该装置包括开关电阻阵列，每个开关电阻器用于接收控制信号，其中开关电阻阵列产生输出信号; 以及配置输出信号相位角的电路。 该装置可用于不同的封装和电感器配置。 该装置通过调整相位角度提供了减轻开关噪声的灵活性，并提供了在无飞舞时启用和禁用开关电阻的能力。 该装置还通过在禁用相位时选择性地关闭开关电阻来节省功耗。 该装置的输出信号具有平滑的三角波形，用于提高使用输出信号产生的电源的质量。 总体而言，与传统的信号发生器相比，该装置对于工艺变化的敏感度降低。
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4.发明授权
公开(公告)号：EP2446534B1
公开(公告)日：2015-01-07
申请号：EP10752360.7
申请日：2010-06-21
申请人： Centre National de la Recherche Scientifique (CNRS) , Commissariat à l'Énergie Atomique et aux Énergies Alternatives , Université Paris-Sud
IPC分类号： H03H11/26
CPC分类号： H03H11/26
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5.发明公开
公开(公告)号：EP2446534A2
公开(公告)日：2012-05-02
申请号：EP10752360.7
申请日：2010-06-21
申请人： Centre National de la Recherche Scientifique (C.N.R.S.) , Commissariat à l'Énergie Atomique et aux Énergies Alternatives , Université Paris-Sud 11
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： The invention relates to a device comprising a binary pulse input signal converting means (3, 4), the output of which is connected to a means forming a counter (6) and to a means forming a delay line (7) that comprises a plurality of delay elements, the means forming a counter (6) and the means forming a delay line (7) also receiving a clock signal (8) as an input, characterized in that the means forming a delay line (7) is combined with a means forming a sampler and analog memory (9) comprising a plurality of storage cells that receive the input signal (1) as input, and in that each element of the means forming a delay line (7) has an output connected to a corresponding storage cell of the means forming analog memory (9) so as to sequentially control the sampling and storage of the input signal (1) in the latter.
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公开(公告)号：EP1716639A2
公开(公告)日：2006-11-02
申请号：EP05706041.0
申请日：2005-01-25
申请人： MOTOROLA, INC.
IPC分类号： H03H11/26
CPC分类号： H03L7/0802 , H03K5/133 , H03K2005/00019 , H03L7/0812 , H03L7/0814 , H03L7/16
摘要： A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18,…, 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
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公开(公告)号：EP1673861A1
公开(公告)日：2006-06-28
申请号：EP04794283.4
申请日：2004-10-05
申请人： ATMEL CORPORATION
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A vernier time shifting circuit 100 is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit 100 allows shifting the signal in small steps to allow for optimal sampling. Various amounts of delay of the time-shifted signal are available at a plurality of output delay taps 113.
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公开(公告)号：EP0607630B1
公开(公告)日：1999-03-17
申请号：EP93203471.3
申请日：1993-12-10
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9.发明公开CMOS multi-tap digital delay line with non-inverting taps 失效Mit mehreren nicht-invertierenden Abgriffen versehene，digitale CMOS-Verzögerungsleitung。
公开(公告)号：EP0606979A2
公开(公告)日：1994-07-20
申请号：EP94300061.2
申请日：1994-01-06
摘要： A programmable digital delay line having N delay elements, two multiplexer connected to the output of the delay elements, and a comparator connected to the outputs of the multiplexers is disclosed. The invention teaches an apparatus and a method of delaying a signal, while reducing the number of delay elements and the number of connections to multiplexers. In a first embodiment of the invention, the delay elements are inverters or differential delay elements. In a second embodiment, the delay elements are differential delay elements.
摘要翻译： 公开了一种具有N个延迟元件的可编程数字延迟线，连接到延迟元件的输出的两个多路复用器以及连接到多路复用器的输出的比较器。 本发明教导了一种延迟信号的装置和方法，同时减少延迟元件的数量和与多路复用器的连接数量。 在本发明的第一实施例中，延迟元件是逆变器或差分延迟元件。 在第二实施例中，延迟元件是差分延迟元件。
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公开(公告)号：EP0600141A1
公开(公告)日：1994-06-08
申请号：EP92830602.6
申请日：1992-10-30
CPC分类号： H03F3/45071 , H03F1/3211 , H03H11/0422
摘要： A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal, e.g. the emitter terminal, in common.
摘要翻译： 一种用于在低电压电源上操作的高频滤波器的跨导器级，其是包括具有信号输入的输入电路部分的类型，还包括一对互连的差分单元（2,3），每一个都与对应的信号输入 。 每个单元包含至少一对双极晶体管（Q1，Q2; Q3，Q4），其具有至少一个相应的端子，例如， 发射极端，共同。
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