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    THREE-TERMINAL INVERTING HYSTERETIC TRANSISTOR SWITCH BACKGROUND OF THE INVENTION
    1.
    发明授权
    THREE-TERMINAL INVERTING HYSTERETIC TRANSISTOR SWITCH BACKGROUND OF THE INVENTION 有权
    反相带三个端子背景技术滞后晶体管开关

    公开(公告)号：EP1329023B1

    公开(公告)日：2007-05-09

    申请号：EP00957252.0

    申请日：2000-07-25

    申请人： CONGDON, James S.

    发明人： CONGDON, James S.

    IPC分类号： H03K3/12

    CPC分类号： H03K3/2893 ,  H03K3/3565 ,  H03K17/30 ,  H03K17/302

    摘要： An Inverting hysteretic transistor switch having an input terminal (13), an output terminal (17) and a ground terminal (15) includes, in some embodiments (11), a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal connected to the output terminal, a gate terminal and a source terminal connected to the ground terminal. The switch further includes a hysteresis circuit (12) connected to the input terminal and to the gate terminal of the MOSFET. In use, with an input voltage having low-to-high and high-to-low input voltage transitions applied to the input terminal, the hysteresis circuit switches the MOSFET to its on switching state at a first threshold voltage during low-to-high input voltage transitions. In addition, the hysteresis circuit switches the MOSFET to its off switching state at a second threshold voltage, which is less than the first threshold voltage, during high-to-low input voltage transitions.

    Correlated sliver latch
    2.
    发明公开
    Correlated sliver latch 失效
    Zueinander在Wechselwirkung stehende geteilteRückkopplungskreise。

    公开(公告)号：EP0401865A2

    公开(公告)日：1990-12-12

    申请号：EP90111017.1

    申请日：1990-06-11

    申请人： DIGITAL EQUIPMENT CORPORATION

    发明人： Samaras, William A. ,  Vaughan, David T.

    IPC分类号： H03K3/02 ,  H03K3/027 ,  H03K3/037 ,  H03K3/289 ,  H03K3/286 ,  H03K3/12 ,  G06F1/025

    CPC分类号： H03K3/037

    摘要： A VSLI circuit includes a plurality of state device circuits on a VLSI chip. Each of the state device circuits includes a latch and is clocked by a pulse generator circuit which produces narrow pulses that are coupled to the clock input of the latch. The narrow pulses have a pulse width substantially equivalent to the propagation delay through the latch of the state device circuits. By taking advantage of the high correlative percentages of devices on portions of the chip, master-slave flip flops can be implemented using only a single latch with a pulse generator.

    摘要翻译： VSLI电路包括VLSI芯片上的多个状态器件电路。 每个状态器件电路包括一个锁存器，并由脉冲发生器电路计时，该脉冲发生器电路产生耦合到锁存器的时钟输入端的窄脉冲。 窄脉冲具有基本上等于通过状态器件电路的锁存器的传播延迟的脉冲宽度。 通过利用芯片部分的器件的高相关百分比，可以仅使用具有脉冲发生器的单个锁存器来实现主从触发器。

    LOW-POWER CMOS FLIP-FLOP
    3.
    发明公开
    LOW-POWER CMOS FLIP-FLOP 审中-公开
    CMOS FLIP具有低功耗FLOPS

    公开(公告)号：EP1490969A4

    公开(公告)日：2006-07-05

    申请号：EP03716979

    申请日：2003-04-04

    申请人： UNIV MICHIGAN

    发明人： ZIESLER CONRAD H ,  PAPAEFTHYMIOU MARIOS C

    IPC分类号： H03K3/356 ,  H03K3/037 ,  H03K3/12 ,  H03K3/286

    CPC分类号： H03K3/356121

    摘要： A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).

    SINGLE ENDED INTERCONNECT SYSTEMS
    4.
    发明公开
    SINGLE ENDED INTERCONNECT SYSTEMS 审中-公开
    非对称链路系统

    公开(公告)号：EP1135856A1

    公开(公告)日：2001-09-26

    申请号：EP99951415.1

    申请日：1999-09-10

    申请人： INTEL CORPORATION

    发明人： KRISHNAMURTHY, Ram, K. ,  SOUMYANATH, Krishnamurthy

    IPC分类号： H03K3/12 ,  H03K3/286

    CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

    摘要： In some embodiments, the invention includes an interconnect system (50) having a single ended driver (54) and single ended hysteretic receiver (58). A single ended interconnect (66) is coupled between the single ended driver and single ended receiver. In other embodiments (figure 4), the invention involves an interconnect system including interconnects (66A, 66B), single ended drivers (54A, 54B), and single ended hysteretic receivers (58A, 58B) connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals (Din(0), Din(1)) and an enable signal (Enable) and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted. In yet other embodiments (140), the invention includes an interconnect system having interconnects (66A, 66B), quasi-static drivers (142A, 142B) and receivers (150A, 150B) connected to respective ones of the interconnects, the quasi-static drivers receive a clock signal (CLK) and respective data-in signals (Din(0), Din(1)), and wherein the interconnect signals are pre-discharged when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals. In still other embodiments, the invention includes a pseudo differential interconnect system (90) and an interconnect system with a dual rail driver (190).

    Flip-flop circuit
    5.
    发明公开
    Flip-flop circuit 失效
    触发器电路

    公开(公告)号：EP0403215A3

    公开(公告)日：1993-07-21

    申请号：EP90306371.7

    申请日：1990-06-12

    申请人： NEC CORPORATION

    发明人： Tago, Shusei

    IPC分类号： H03K3/286 ,  H03K3/289 ,  H03K3/2885 ,  H03K3/12

    CPC分类号： H03K3/289 ,  H03K3/2885

    摘要： A Flip-Flop circuit, of a current-pass switching type logical circuit, of the invention comprises a pair of data holding transistors (Q₁₁,Q₁₂), the emitters thereof being tied together at a first junction point (22) and being led to a constant-current source (18); and a set signal input transistor (Q₁₈) and a reset signal input transistor (Q₁₉), the emitters thereof being tied together at a second junc­tion point (21) and being led to the constant-current source. There is provided a single level-shifting resistor (20) between the first junction point (22) and the second junction point (21) for preventing interference or concur­rence between the high level of a set signal or a reset signal and the high level of the internal data held by the data holding transistors (Q₁₁,Q₁₂). The circuit is suit­able to be fabricated in a semiconductor integrated circuit device of high packing density. The working range of power supply voltages for the circuit is wide because the level shift voltage developed across the level-shifting resistor is not influenced by the variation of the power supply voltage.

    摘要翻译： 本发明的电流通道切换型逻辑电路的触发器电路包括一对数据保持晶体管（Q 11，Q 12），它们的发射极在第一连接点（22）处连接在一起并被引导到 一个恒流源（18）; 和一个置位信号输入晶体管（Q 18）和一个复位信号输入晶体管（Q 18），它们的发射极在第二个连接点（21）连接在一起并被引导到恒流源。 在第一接合点（22）和第二接合点（21）之间提供了单个电平移动电阻器（20），用于防止设置信号的高电平或复位信号与高电平之间的干扰或并发 由数据保持晶体管（Q 11，Q 12）保持的内部数据。 该电路适合于制造在高封装密度的半导体集成电路器件中。 电路的电源电压的工作范围很宽，因为在电平移动电阻上产生的电平移动电压不受电源电压变化的影响。

    THREE-TERMINAL INVERTING HYSTERETIC TRANSISTOR SWITCH BACKGROUND OF THE INVENTION
    6.
    发明公开
    THREE-TERMINAL INVERTING HYSTERETIC TRANSISTOR SWITCH BACKGROUND OF THE INVENTION 有权
    反相带三个端子背景技术滞后晶体管开关

    公开(公告)号：EP1329023A4

    公开(公告)日：2005-12-07

    申请号：EP00957252

    申请日：2000-07-25

    申请人： CONGDON JAMES S

    发明人： CONGDON JAMES S

    IPC分类号： H03K5/08 ,  H03K3/2893 ,  H03K3/3565 ,  H03K17/30 ,  H03K3/12

    CPC分类号： H03K3/2893 ,  H03K3/3565 ,  H03K17/30 ,  H03K17/302

    摘要： An Inverting hysteretic transistor switch having an input terminal (13), an output terminal (17) and a ground terminal (15) includes, in some embodiments (11), a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal connected to the output terminal, a gate terminal and a source terminal connected to the ground terminal. The switch further includes a hysteresis circuit (12) connected to the input terminal and to the gate terminal of the MOSFET. In use, with an input voltage having low-to-high and high-to-low input voltage transitions applied to the input terminal, the hysteresis circuit switches the MOSFET to its on switching state at a first threshold voltage during low-to-high input voltage transitions. In addition, the hysteresis circuit switches the MOSFET to its off switching state at a second threshold voltage, which is less than the first threshold voltage, during high-to-low input voltage transitions.

    THREE-TERMINAL INVERTING HYSTERETIC TRANSISTOR SWITCH BACKGROUND OF THE INVENTION
    7.
    发明公开
    THREE-TERMINAL INVERTING HYSTERETIC TRANSISTOR SWITCH BACKGROUND OF THE INVENTION 有权
    反相带三个端子背景技术滞后晶体管开关

    公开(公告)号：EP1329023A1

    公开(公告)日：2003-07-23

    申请号：EP00957252.0

    申请日：2000-07-25

    申请人： CONGDON, James S.

    发明人： CONGDON, James S.

    IPC分类号： H03K3/12

    CPC分类号： H03K3/2893 ,  H03K3/3565 ,  H03K17/30 ,  H03K17/302

    摘要： An Inverting hysteretic transistor switch having an input terminal (13), an output terminal (17) and a ground terminal (15) includes, in some embodiments (11), a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal connected to the output terminal, a gate terminal and a source terminal connected to the ground terminal. The switch further includes a hysteresis circuit (12) connected to the input terminal and to the gate terminal of the MOSFET. In use, with an input voltage having low-to-high and high-to-low input voltage transitions applied to the input terminal, the hysteresis circuit switches the MOSFET to its on switching state at a first threshold voltage during low-to-high input voltage transitions. In addition, the hysteresis circuit switches the MOSFET to its off switching state at a second threshold voltage, which is less than the first threshold voltage, during high-to-low input voltage transitions.

    Flip-flop circuit
    8.
    发明公开
    Flip-flop circuit 失效
    触发器，Schaltkreis。

    公开(公告)号：EP0403215A2

    公开(公告)日：1990-12-19

    申请号：EP90306371.7

    申请日：1990-06-12

    申请人： NEC CORPORATION

    发明人： Tago, Shusei

    IPC分类号： H03K3/286 ,  H03K3/289 ,  H03K3/2885 ,  H03K3/12

    CPC分类号： H03K3/289 ,  H03K3/2885

    摘要： A Flip-Flop circuit, of a current-pass switching type logical circuit, of the invention comprises a pair of data holding transistors (Q₁₁,Q₁₂), the emitters thereof being tied together at a first junction point (22) and being led to a constant-current source (18); and a set signal input transistor (Q₁₈) and a reset signal input transistor (Q₁₉), the emitters thereof being tied together at a second junc­tion point (21) and being led to the constant-current source. There is provided a single level-shifting resistor (20) between the first junction point (22) and the second junction point (21) for preventing interference or concur­rence between the high level of a set signal or a reset signal and the high level of the internal data held by the data holding transistors (Q₁₁,Q₁₂). The circuit is suit­able to be fabricated in a semiconductor integrated circuit device of high packing density. The working range of power supply voltages for the circuit is wide because the level shift voltage developed across the level-shifting resistor is not influenced by the variation of the power supply voltage.

    摘要翻译： 本发明的电流通切换型逻辑电路的触发器电路包括一对数据保持晶体管（Q11，Q12），其发射极在第一连接点（22）处被连接在一起，并被引导到 恒流源（18）; 和设置信号输入晶体管（Q18）和复位信号输入晶体管（Q19），其发射极在第二连接点（21）处连接在一起并被引导到恒流源。 在第一连接点（22）和第二连接点（21）之间提供单个电平移动电阻（20），用于防止设定信号或复位信号的高电平与高电平 由数据保持晶体管（Q11，Q12）保持的内部数据。 该电路适合于在高封装密度的半导体集成电路器件中制造。 电路电源电压的工作范围很宽，因为电平移动电阻上产生的电平转换电压不受电源电压变化的影响。