公开(公告)号：JP2003069402A

公开(公告)日：2003-03-07

申请号：JP2001252859

申请日：2001-08-23

Applicant: Denso Corp ,  株式会社デンソー

Inventor： KOYAMA YOSHINORI ,  UEDA NOBUTADA ,  FUJIMOTO YUTAKA

IPC: H03K17/16 ,  H03K17/567

Abstract: PROBLEM TO BE SOLVED: To reduce waveform distortion caused when reduction of a trapezoidal wave load current is started.
SOLUTION: A clamp circuit 23 is provided between a source of a transistor Q11 acting like a high side switch and an output node n2 of an operational amplifier configuring an error amplifier circuit 31. When a drive command signal changes from an H level to an L level, transistors Q18, Q17 are turned on and a voltage Vn2 at a node n2 having increased up to a boosting voltage Vcp is decreased to a Zener voltage Vz of a Zener diode D11 by using a level VL of a load terminal 20 as a reference level. The Zener voltage Vz is a value higher than a threshold voltage Vt of the transistor Q11 and close to the threshold voltage Vt. Thus, gate electric charges of the transistor Q11 are extracted through a transistor Q16 and a load current IL immediately decreases according to a trapezoidal waveform signal Sb.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了减少在梯形波负载电流的减小开始时引起的波形失真。 解决方案：钳位电路23设置在类似于高侧开关的晶体管Q11的源极和构成误差放大器电路31的运算放大器的输出节点n2之间。当驱动命令信号从H电平变为L 晶体管Q18，Q17导通，并且通过使用负载端子20的电平VL作为参考，将增加到升压电压Vcp的节点n2处的电压Vn2降低到齐纳二极管D11的齐纳电压Vz 水平。 齐纳电压Vz是高于晶体管Q11的阈值电压Vt并且接近阈值电压Vt的值，因此晶体管Q11的栅极电荷通过晶体管Q16提取，负载电流IL根据 梯形波形信号Sb。

公开(公告)号：JP2002344297A

公开(公告)日：2002-11-29

申请号：JP2001147714

申请日：2001-05-17

Applicant: DENSO CORP

Inventor： TSUCHIDA MASAHIRO ,  KOYAMA YOSHINORI ,  UEDA NOBUTADA ,  FUJIMOTO YUTAKA

IPC: H03K17/14 ,  H03K17/567

Abstract: PROBLEM TO BE SOLVED: To match conduction time of an electrical load being command to an actual conduction time, regardless of the magnitude of impedance of the electrical load. SOLUTION: A current control circuit 20 controls the gate potential of a transistor Q11, such that a load current IL and a trapezoidal wave signal Sb coincide with each other. When a drive command signal Sa goes to H, the trapezoidal wave signal Sb increases with a constant inclination, and when the transistor Q11 operates in a linear region due to increase of the load current IL, the gate voltage VGS increases abruptly. A saturation state detecting circuit 21 brings a current saturation signal Sc to L, at a moment when the gate voltage VGS exceeds a reference voltage Vr, and in response thereto, a trapezoidal wave generating circuit 19 stops increase of the trapezoidal wave signal Sb and holds the trapezoidal wave signal Sb. When the drive command signal Sa goes to L, the trapezoidal wave signal Sb decreases with a fixed slope, and the load current IL follows up the trapezoidal wave signal Sb and decreases.

公开(公告)号：JP2001308195A

公开(公告)日：2001-11-02

申请号：JP2000118319

申请日：2000-04-19

Applicant: DENSO CORP

Inventor： KOYAMA YOSHINORI ,  UEDA NOBUTADA ,  FUJIMOTO YUTAKA

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which current control of a load drive circuit can be carried out with high accuracy. SOLUTION: A substantially square shape is constituted of the drain cells 10 and source cells 11 of a main LDMOS and a sense LDMOS and the drain cells 11 of the sense LDMOS are arranged to pass through both the central part and the corner parts of the substantially square shape. More specifically, they are arranged such that the drain lead wires 13 for the sense LDMOS form one diagonal of the substantially square shape. Consequently, variation in the ON resistance of LDMOS arranged at the corners of the substantially square shape and variation in the ON resistance of LDMOS arranged in the central part of the substantially square shape are averaged and can be taken out as a detection value. Since variations in the ON resistance can be prevented and the current mirror ratio can be prevented from being shifted, current control of a load drive circuit can be carried out with high accuracy.

公开(公告)号：JP2003069403A

公开(公告)日：2003-03-07

申请号：JP2001254402

申请日：2001-08-24

Applicant: Denso Corp ,  株式会社デンソー

Inventor： KOYAMA YOSHINORI ,  TSUCHIDA MASAHIRO ,  UEDA NOBUTADA ,  FUJIMOTO YUTAKA

IPC: H03K17/16 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a driver or supplying a trapezoidal waveform current to an electric load so as to furthermore decrease a noise caused by power application/interruption.
SOLUTION: A trapezoidal wave generating circuit 21 generates a trapezoidal wave signal Sb according to a drive command signal Sa. A current control circuit 22 controls a MOS transistor Q11 to supply a load current IL equal to the trapezoidal wave signal Sb. A measurement circuit 23 measures a leading time and a trailing time of a voltage across a load I2 in proportional relation to the load current IL, and a gradation control circuit 24 controls a gradual increasing ratio and a gradual decreasing ratio of the trapezoidal wave signal Sb so that the leading time and the trailing time are respectively equal to a reference leading time Ta and a reference trailing time Tb. Clamp circuits 58, 59 limits a rate of change in the trapezoidal wave signal Sb so as not exceed a limit value.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供驱动器或向电负载提供梯形波形电流，以进一步降低由施加电力/中断引起的噪声。 解决方案：梯形波发生电路21根据驱动指令信号Sα产生梯形波信号Sb。 电流控制电路22控制MOS晶体管Q11以提供等于梯形波信号Sb的负载电流IL。 测量电路23测量与负载电流IL成比例的负载I2两端的电压的前导时间和拖尾时间，灰度控制电路24控制梯形波信号Sb的逐渐增加率和逐渐减小的比例 使得引导时间和拖尾时间分别等于参考引导时间Ta和参考结束时间Tb。 钳位电路58,59限制梯形波信号Sb的变化率不超过极限值。

公开(公告)号：JPH09266310A

公开(公告)日：1997-10-07

申请号：JP25029996

申请日：1996-09-20

Applicant: DENSO CORP

Inventor： FUJIMOTO YUTAKA ,  SAITO MITSUHIRO ,  IMAI YUSHI ,  BAN HIROYUKI

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To suppress the voltage level deviation at the time of driving a load and the generation of switching noise by surrounding the circumference of semiconductor element formed on an element region that is insulated to separate the fixed potential region. SOLUTION: In element regions that are separated to island form by an oxide film 23, cell regions that are formed with lateral diffused MOS transistors(LDMOS) are arranged and around the cell regions, a P well 29 that fixes the potential of a P well 16 at the level of source potential is arranged. Around the circumference of it, a deep N diffused layer 26 is formed in contact with the oxide film 23. A bottom electrode B is connected to the deep N diffused layer 26, and the potentials of the deep N diffused layer 26 and an N substrate 21b are fixed by fixing the potential of the bottom electrode B. Though there exists a parasitic capacitance 32 at an insulating film 22, the deviation of the potential of a P type substrate 20 can be suppressed when the LDMOS operates switching operation, by fixing the potentials of the deep N diffused layer 26 and the N substrate 21b.

公开(公告)号：JP2005039543A

公开(公告)日：2005-02-10

申请号：JP2003274734

申请日：2003-07-15

Applicant: Denso Corp ,  株式会社デンソー

Inventor： UEDA NOBUTADA ,  FUJIMOTO YUTAKA ,  MATSUOKA TOSHIHIKO ,  YAMAMOTO SEI

IPC: H04L25/03

Abstract: PROBLEM TO BE SOLVED: To provide a transceiver device reducing a noise generated accompanying communications.
SOLUTION: In a transceiver 21 at a master side and transceivers 22-25 at a slave side, each connected to a network for an automobile, each communication rate detection circuit 27 detects a communication rate by measuring the specified period of time in the synchronous field of reception data outputted from a reception circuit 11. Each gradient generation circuit 33 generates a trapezoidal wave-like driving instruction signal by using a CR integrating circuit, where, the trapezoidal wave-like driving instruction signal is generated by dulling the a change in the edge of transmission data. Thus, the rate of change of a data signal on a communication bus 3 is automatically adjusted to a value complying with the actual communication rate to reduce the rate of change of the edge when the communication rate is set to a low value, reducing the noise (radio noise) radiated from the communication bus 3.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种减少伴随通信产生的噪声的收发器装置。 解决方案：在主机侧的收发器21和从机侧的收发器22-25，各自连接到用于汽车的网络，每个通信速率检测电路27通过测量指定的时间段来检测通信速率 从接收电路11输出的接收数据的同步场。梯度生成电路33通过使用CR积分电路生成梯形波状的驱动指示信号，其中，梯形波状驱动指令信号通过使a 改变传输数据的边缘。 因此，通信总线3上的数据信号的变化率被自动调整为符合实际通信速率的值，以在通信速率被设置为低值时降低边缘的变化率，从而降低噪声 （无线电噪声）。3.版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002251885A

公开(公告)日：2002-09-06

申请号：JP2001046466

申请日：2001-02-22

Applicant: DENSO CORP

Inventor： OKUNO TAKUYA ,  FUJIMOTO YUTAKA ,  IWAMORI NORIYUKI

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory capable of enhancing read-out precision with a new configuration. SOLUTION: In a read-out circuit 10, when a transistor is in a off-state in the consequence of that read-out performed for memory transistors T01-T03 in a memory block cell block X, a switch S2 is turned on, and substrate bias voltage is applied to memory transistors T11-T13 of a memory cell block Y. In a read-out circuit 11, when a transistor is in a off-state in the consequence of that read-out is performed for memory transistors T11-T13 in a memory block cell book Y, a switch S1 is turned on, and substrate bias voltage is applied to the memory transistors T01-T03 of the memory cell block X.