公开(公告)号：JP2009118546A

公开(公告)日：2009-05-28

申请号：JP2007285419

申请日：2007-11-01

Applicant: Denso Corp ,  株式会社デンソー

Inventor： MIYAWAKI SEITARO ,  UEDA NOBUTADA

IPC: H02H3/05 ,  G05F1/10 ,  H02H7/20

Abstract: PROBLEM TO BE SOLVED: To detect the fault of a transistor for current detection, which is connected in parallel with a power transistor for supplying a load with a current, in simple structure. SOLUTION: In a power transistor circuit, first and second transistors 2 and 3 for current detection are connected in parallel with a power transistor 1. It determines whether the difference between the first and second voltage signals V1 and V2 equivalent to the values of first and second currents flowing in these first and second transistors 2 and 3 for current detection is settled in a predetermined range or not. From the determination results, it can detect the faulty state of either of the first and second transistors for current detection. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：以简单的结构检测与用于向负载供电的功率晶体管并联连接的电流检测用晶体管的故障。 解决方案：在功率晶体管电路中，用于电流检测的第一和第二晶体管2和3与功率晶体管1并联连接。它确定第一和第二电压信号V1和V2之间的差是否等于值 在这些用于电流检测的第一和第二晶体管2和3中流动的第一和第二电流被确定在预定范围内。 从确定结果可以检测用于电流检测的第一和第二晶体管中的任一个的故障状态。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007305905A

公开(公告)日：2007-11-22

申请号：JP2006134967

申请日：2006-05-15

Applicant: Denso Corp ,  株式会社デンソー

Inventor： TOBITAKA KOMEI ,  AZUMA HIDEJI ,  UEDA NOBUTADA

IPC: H01L21/76 ,  H01L21/66 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To materialize an inspection apparatus and an inspection method of an insulation isolated semiconductor device which can certainly detect insulation failure in an insulator which performs insulated isolation of an insulation isolated semiconductor device. SOLUTION: A predetermined voltage is applied to a first and a second voltage applied pads 20c and 30c by contacting a first and a second voltage applying probes 41 and 42 respectively, so as to detect the current which flows between an element formation region 20 and an isolation region 30. Furthermore, the electrical connection between a second voltage applied pad 30c and a second inspection applying probe 42 is detected by detecting the voltage between a second voltage applying probe 42 and an inspection probe 43, while contacting the inspection probe 43 with an inspection pad 31c. When current is not detected and electrical connection is detected, it is judged that the relation between the element formation region 20 and the isolation region 30 is in an insulated state. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：实现绝缘隔离半导体器件的检查装置和检查方法，绝缘隔离半导体器件能够绝对地检测绝缘体的隔离故障，绝缘体进行绝缘隔离半导体器件的绝缘隔离。 解决方案：通过分别接触第一和第二电压施加探针41和42，将预定电压施加到第一和第二电压施加焊盘20c和30c，以便检测在元件形成区域 20和隔离区30.此外，通过检测第二电压施加探针42和检查探针43之间的电压，同时接触检查探针来检测第二施加电压垫30c和第二检查施加探针42之间的电连接 43与检查垫31c。 当没有检测到电流并且检测到电连接时，判断元件形成区域20和隔离区域30之间的关系处于绝缘状态。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007174565A

公开(公告)日：2007-07-05

申请号：JP2005372814

申请日：2005-12-26

Applicant: Denso Corp ,  株式会社デンソー

Inventor： UEDA NOBUTADA

IPC: H03F1/48 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/082 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor circuit device where a differential amplifier circuit is formed, wherein a circuit operating speed can be made compatible with stability, and it is manufactured at a low cost without limitation of application circuits.
SOLUTION: The semiconductor circuit device 100 is constituted so that a current supply transistor Q3p supplying a bias current Ib to two input transistors Q1, Q2 in a differential amplifier circuit 100a is comprised of a bipolar transistor of a multi-collector, a first collector c
1 of the current supply transistor Q3p is connected in common to emitters of the two input transistors Q1, Q2, and between the first collector c
1 and a second collector c
2 of the current supply transistor Q3p, a parasitic resistor Rp is formed, and in a state where there is no input to the two input transistors Q1, Q2, the second collector c
2 is set to the identical potential to the first collector c
1 .
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供形成差分放大器电路的半导体电路器件，其中电路工作速度可以与稳定性兼容，并且以低成本制造而不受应用电路的限制。 解决方案：半导体电路器件100被构造成使得向差分放大器电路100a中的两个输入晶体管Q1，Q2提供偏置电流Ib的电流源晶体管Q3p由多极集电极的双极晶体管， 电流源晶体管Q3p的第一集电极c 1 共同连接到两个输入晶体管Q1，Q2的发射极，并且在第一集电极c 1 和第二集电极 电流晶体管Q3p的c 2 ，形成寄生电阻器Rp，在两个输入晶体管Q1，Q2没有输入的状态下，第二集电极c / SB>被设定为与第一收集器c 1 相同的电位。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006019871A

公开(公告)日：2006-01-19

申请号：JP2004193558

申请日：2004-06-30

Applicant: Denso Corp ,  株式会社デンソー

Inventor： NUMAZAKI KOJI ,  UEDA NOBUTADA ,  KASUYA KOICHI

IPC: H03K3/0231

Abstract: PROBLEM TO BE SOLVED: To provide an electronic apparatus incorporating a CR oscillation circuit for generating a clock signal with high oscillation accuracy. SOLUTION: A microcomputer 2 including a clock terminal 2a and activated with a clock signal with a prescribed operating frequency received from the clock terminal 2a, and a CR oscillation circuit 60 for generating a signal with an oscillation frequency based on a time constant comprising capacitance of a capacitor 61 and resistance of a resistor 62 and supplying the generated signal to the clock terminal 2a of the microcomputer 2, are mounted on a board as respective integrated circuit components. The resistor of the CR oscillation circuit 60 is subjected to laser trimming so that the oscillation frequency of the signal generated by the CR oscillation circuit 60 reaches the prescribed operating frequency. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种结合CR振荡电路的电子装置，用于产生具有高振荡精度的时钟信号。 解决方案：包括时钟端子2a并由从时钟端子2a接收的具有规定工作频率的时钟信号激活的微型计算机2以及用于基于时间常数产生具有振荡频率的信号的CR振荡电路60 包括电容器61的电容和电阻62的电阻并将产生的信号提供给微型计算机2的时钟端子2a，作为各自的集成电路部件安装在板上。 对CR振荡电路60的电阻进行激光微调，使得由CR振荡电路60产生的信号的振荡频率达到规定的工作频率。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006011499A

公开(公告)日：2006-01-12

申请号：JP2004183264

申请日：2004-06-22

Applicant: Denso Corp ,  株式会社デンソー

Inventor： KAWAMOTO IPPEI ,  UEDA NOBUTADA

IPC: G05F1/10 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a DC power unit having a standby mode and an active mode for preventing an output voltage from being temporarily lowered due to the influence of an internal capacitor for phase compensation when switching the standby mode to the active mode.
SOLUTION: A power source (2a) for active mode to be controlled by an output transistor (Q1) in which the output of an error amplifier (OP1) having a capacitor (C1) for phase compensation whose one end is connected to the output terminal (12) is received through a first switch (SW1) by the control terminal (16) and a power source (3) for standby mode are switched, and power supply is executed. When the operation of the power source for active mode is stopped, the first switch is put in a non-conductive status, and the potential of the output terminal of the error amplifier is maintained as a value equal to the potential of the output terminal in the regular operation of the power source for active mode by an auxiliary constant voltage source (Eo).
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种具有待机模式和有功模式的直流电源单元，用于在将待机模式切换到活动状态时，防止输出电压由于用于相位补偿的内部电容器的影响而暂时降低 模式。 解决方案：用于主动模式的电源（2a）由输出晶体管（Q1）控制，在该输出晶体管（Q1）中，具有用于相位补偿的电容器（C1）的误差放大器（OP1）的输出端连接到 通过控制端子（16）通过第一开关（SW1）接收输出端子（12），切换用于待机模式的电源（3），并且执行电源。 当停止用于主动模式的电源的操作时，第一开关处于非导通状态，并且将误差放大器的输出端子的电位维持为等于输出端子的电位的值 通过辅助恒压源（Eo）对主动模式的电源进行常规操作。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003078401A

公开(公告)日：2003-03-14

申请号：JP2001263493

申请日：2001-08-31

Applicant: Denso Corp ,  株式会社デンソー

Inventor： UEDA NOBUTADA

IPC: G05F1/56 ,  H03K17/16 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a controller of a power MOS transistor capable of suppressing noise and heat generation with a new configuration.
SOLUTION: The power MOS transistor 1 and a load 2 are serially connected to a power source Vcc, and voltage is applied to a gate terminal of the power MOS transistor 1 to cause current of a pulse shape in which a rise and a fall become in a slope shape to flow to the load 2. A circuit 5 for detecting voltage between a gate and a source detects voltage Vgs between a gate and a source of the power MOS transistor in accordance with voltage application to a gate terminal of the power MOS transistor. A control logic 4 calculates deviation between rise and fall times Tup and Tdown and a target value in a conductive current waveform of the load 2 of this time from the voltage Vgs between the gate and the source and performs feedback control of the power MOS transistor so as to eliminate the deviation.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种能够通过新的结构抑制噪声和发热的功率MOS晶体管的控制器。 解决方案：功率MOS晶体管1和负载2串联连接到电源Vcc，并且电压施加到功率MOS晶体管1的栅极端子，以使上升和下降的脉冲形状的电流 用于检测栅极和源极之间的电压的电路5根据向功率MOS晶体管的栅极端子施加的电压来检测功率MOS晶体管的栅极和源极之间的电压Vgs 。 控制逻辑4根据栅极和源极之间的电压Vgs计算上升和下降时间Tup和Tdown之间的偏差以及此时负载2的导电电流波形中的目标值，并执行功率MOS晶体管的反馈控制 以消除偏差。

公开(公告)号：JP2003069403A

公开(公告)日：2003-03-07

申请号：JP2001254402

申请日：2001-08-24

Applicant: Denso Corp ,  株式会社デンソー

Inventor： KOYAMA YOSHINORI ,  TSUCHIDA MASAHIRO ,  UEDA NOBUTADA ,  FUJIMOTO YUTAKA

IPC: H03K17/16 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a driver or supplying a trapezoidal waveform current to an electric load so as to furthermore decrease a noise caused by power application/interruption.
SOLUTION: A trapezoidal wave generating circuit 21 generates a trapezoidal wave signal Sb according to a drive command signal Sa. A current control circuit 22 controls a MOS transistor Q11 to supply a load current IL equal to the trapezoidal wave signal Sb. A measurement circuit 23 measures a leading time and a trailing time of a voltage across a load I2 in proportional relation to the load current IL, and a gradation control circuit 24 controls a gradual increasing ratio and a gradual decreasing ratio of the trapezoidal wave signal Sb so that the leading time and the trailing time are respectively equal to a reference leading time Ta and a reference trailing time Tb. Clamp circuits 58, 59 limits a rate of change in the trapezoidal wave signal Sb so as not exceed a limit value.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供驱动器或向电负载提供梯形波形电流，以进一步降低由施加电力/中断引起的噪声。 解决方案：梯形波发生电路21根据驱动指令信号Sα产生梯形波信号Sb。 电流控制电路22控制MOS晶体管Q11以提供等于梯形波信号Sb的负载电流IL。 测量电路23测量与负载电流IL成比例的负载I2两端的电压的前导时间和拖尾时间，灰度控制电路24控制梯形波信号Sb的逐渐增加率和逐渐减小的比例 使得引导时间和拖尾时间分别等于参考引导时间Ta和参考结束时间Tb。 钳位电路58,59限制梯形波信号Sb的变化率不超过极限值。

公开(公告)号：JP2009230421A

公开(公告)日：2009-10-08

申请号：JP2008074390

申请日：2008-03-21

Applicant: Denso Corp ,  株式会社デンソー

Inventor： FUKATSU AKIHIRO ,  UEDA NOBUTADA

IPC: G05F1/10 ,  G01R19/00 ,  G05F1/56

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for providing a load current that can prevent deterioration in the accuracy in detecting a current, to the utmost, even if the temperature varies. SOLUTION: A thick-film resistor R6 whose resistance value is adjustable is connected in series to a transistor Tr2 for detecting a current that is connected to a power transistor Tr1 in parallel. This thick-film resistor R6 has a property that it varies the resistance value with the temperature. Thus, a trimming adjustment of the resistance value of the thick-film resistor R6 enables the circuit to substantially match the ratio of variation in resistance value due to a thermal property of a path, through which the load current I1 flows via the power transistor Tr1 with the ratio of variation in resistance value due to the thermal property of a path via which a current I2 for detection flows via the transistor Tr2 for detecting a current. This enables the ratio between the load current I1 and the current I2 for detection to be kept substantially at a prescribed ratio, even if the temperature varies, thereby allowing the load current I1 to be detected accurately, on the basis of the current I2 for detection. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种用于提供可以防止电流检测精度降低的负载电流的电路，即使温度变化也是最大的。 电阻值可调的厚膜电阻R6串联连接到晶体管Tr2，用于检测并联连接到功率晶体管Tr1的电流。 这种厚膜电阻R6具有随着温度改变电阻值的性质。 因此，厚膜电阻器R6的电阻值的修整调整使得电路能够基本上匹配由于负载电流I1经由功率晶体管Tr1流过的路径的热性质导致的电阻值的变化率 其中由于用于检测的电流I2经由用于检测电流的晶体管Tr2流过的路径的热性质导致的电阻值的变化率。 这使得负载电流I1和检测用电流I2之间的比例即使在温度变化的情况下也能够保持基本上为规定的比例，从而能够根据检测用电流I2来准确地检测负载电流I1 。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008193800A

公开(公告)日：2008-08-21

申请号：JP2007025299

申请日：2007-02-05

Applicant: Denso Corp ,  株式会社デンソー

Inventor： AKAMA SADAHIRO ,  AZUMA HIDEJI ,  UEDA NOBUTADA ,  OSADA KIYOSHI ,  OTAKE AKIYA ,  KURODA MASAHIRO

IPC: H02P6/16 ,  H02M7/00

Abstract: PROBLEM TO BE SOLVED: To solve the following problem: a zero cross timing when an induction voltage of a brushless motor 10 is a reference voltage vref is easily detected by mistake in a situation that the operation speed of the brushless motor 10 varies. SOLUTION: Terminal voltages vu, vv, vw of phases are respectively compared with the reference voltage vref in comparators Cur, Cvr, Cwr, compared with a positive pole voltage VB of a battery 14 in comparators Cub, Cvb, Cwb, and compared with a negative pole voltage of the battery 14 in comparators Cug, Cvg, Cwg. Logical OR circuits ORu, ORv, ORw generate logic reverse signals of output signals of the comparators Cug, Cvg, Cwg, and generate mask signals mu, mv, vw on the basis of the output signals of the comparators Cub, Cvb, Cwb. Exclusive OR circuits EXu, EXv, EXw generate comparison signals pu, pv, pw on the basis of temporary comparison signals pu0, pv0, pw0 outputted from the comparators Cur, Cvr, Cwr and the mask signals mu, mv, vw. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决以下问题：在无刷电动机10的运转速度变化的情况下，容易检测无刷电动机10的感应电压为基准电压vref时的零交叉定时 。 解决方案：与比较器Cub，Cvb，Cwb和...中的电池14的正极电压VB相比，相位的端子电压vu，vv，vw分别与比较器Cur，Cvr，Cwr中的参考电压vref进行比较 与比较器Cug，Cvg，Cwg中的电池14的负极电压相比。 逻辑OR电路ORu，ORv，ORw产生比较器Cug，Cvg，Cwg的输出信号的逻辑反向信号，并且基于比较器Cub，Cvb，Cwb的输出信号生成屏蔽信号mu，mv，vw。 基于从比较器Cur，Cvr，Cwr和掩蔽信号mu，mv，vw输出的临时比较信号pu0，pv0，pw0，异或电路EXu，EXv，EXw产生比较信号pu，pv，pw。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008148379A

公开(公告)日：2008-06-26

申请号：JP2006329430

申请日：2006-12-06

Applicant: Denso Corp ,  株式会社デンソー

Inventor： UEDA NOBUTADA ,  AZUMA HIDEJI ,  AKAMA SADAHIRO ,  KURODA MASAHIRO ,  OSADA KIYOSHI ,  OTAKE AKIYA

IPC: H02P6/18

Abstract: PROBLEM TO BE SOLVED: To provide a motor drive that starts a brushless DC motor, in a short time using a simpler constitution.
SOLUTION: When the motor drive 1 starts a brushless DC motor 2 through forced commutation, a gate drive circuit 5 limits the current flowing through the windings 2U-2W of the motor 2 to the upper limit level, set higher than the level of a current flowing, when the motor 2 goes into steady state steady rotational state.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供使用更简单的结构在短时间内启动无刷DC电动机的电动机驱动。 解决方案：当电机驱动器1通过强制换向启动无刷直流电动机2时，栅极驱动电路5将流过电动机2的绕组2U-2W的电流限制到高于电平的电平 当电机2进入稳态稳定旋转状态时，电流流动。 版权所有（C）2008，JPO＆INPIT