公开(公告)号：JP2002222591A

公开(公告)日：2002-08-09

申请号：JP2001018100

申请日：2001-01-26

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/34

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous semiconductor memory device for which many pieces thereof can be tested simultaneously. SOLUTION: An input/output buffer 80 of the synchronous semiconductor memory device 100 receives a test mode signal from a control circuit 410, takes in data from a terminal 421 synchronizing with a clock signal CLK, writes it in a memory array 60, and outputs read-out data from the memory array 60 to the terminal 421 synchronizing with an internal data strobe signal from a DQS signal generating circuit 70.

公开(公告)号：JP2002117672A

公开(公告)日：2002-04-19

申请号：JP2000308932

申请日：2000-10-10

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI

IPC: G11C11/407

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory in which setting of burst length can be controlled. SOLUTION: A semiconductor memory comprises flip-flop circuits 1, 2, 3, a command discriminating circuit 4A discriminating an inputted command, and a write-in operation control circuit 6. The flip-flop circuit 3 latches a WBL address, when a first write-in command is inputted. The flip-flop circuit 3 holds the WBL address latched in the previous step, when a second write-in command is inputted. The write-in operation control circuit 6 controls the write-in operation, according to burst length indicated by the WBL address outputted by the flip-flop circuit 3.

公开(公告)号：JP2000215662A

公开(公告)日：2000-08-04

申请号：JP925499

申请日：1999-01-18

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI ,  KUBO TAKASHI

IPC: G11C11/407 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory in which current consumption can be reduced. SOLUTION: In a DDRSDRAM(double data rate synchronous dynamic RAM), a mode register 17 which is activated when a signal ϕMA is activated outputs a mode signal MD1-3 according to an address signal ext.A0-j. An inside clock oscillator 18 outputs an inside clock signal int.CLK with frequencies designated by the mode signal MD1-3. Therefore, it is not necessary to provide a clock buffer for the outside clock signal, and it is possible to reduce current consumption.

公开(公告)号：JPH1079663A

公开(公告)日：1998-03-24

申请号：JP23293796

申请日：1996-09-03

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI ,  KONISHI YASUHIRO

IPC: G11C11/407 ,  G06F1/12 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081

Abstract: PROBLEM TO BE SOLVED: To provide an internal clock generating circuit with a wide operating frequency. SOLUTION: This circuit is provided with a variable delay circuit 1 which provides a delay offset to a delay time of a voltage controlled delay element 13a selectively according to a mode switching signal with respect to a voltage controlled element 130 whose delay time is adjusted according to a phase difference between an external clock signal ECLK and an internal clock signal intCLK (RCLK) and generates a signal equivalent to the internal clock signal depending on the adjusted delay time. Thus, the operating speed of the voltage controlled delay element 130 is equivalently slow by the delay offset so as to shift the operating frequency band toward lower frequencies, and accordingly the operating frequency band of the internal clock generating circuit is widened.

公开(公告)号：JPH08221981A

公开(公告)日：1996-08-30

申请号：JP1304895

申请日：1995-01-30

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI ,  KONISHI YASUHIRO ,  DOSAKA KATSUMI ,  MURAI YASUMITSU

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407

Abstract: PURPOSE: To provide a synchronous type semiconductor memory capable of easily writing data by using a high frequency. CONSTITUTION: This semiconductor memory is provided with a changeover switch 3a for connecting two systems of global signal input/output line pair GIO and GIO' and global IO line pair GIO or GIO' to a write-buffer group 60a alternately one clock cycle each and the changeover switch 4a for connecting the global IO line pair GIO' or GIO to an equalization circuit 61a alternately one clock cycle each for a memory array 1a. The data writing through one side global IO line pair GIO and the equalization of the other side global IO line pair GIO' are performed in parallel for one clock cycle.

公开(公告)号：JPH08212778A

公开(公告)日：1996-08-20

申请号：JP2142695

申请日：1995-02-09

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： SAWADA SEIJI ,  KONISHI YASUHIRO ,  IWAMOTO HISASHI

IPC: G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/409

Abstract: PURPOSE: To obtain a synchronous semiconductor memory device in which data can be read out surely in synchronization with a high-speed clock signal. CONSTITUTION: A latch circuit 30 which latches data of two bits or four bits so as to be output one bit by one bit is arranged between a read register group 20 which receives and stores 8-bit data from a sense amplifier group 1 and a 1-bit data output terminal 4. The read register group and the latch circuit 30 output data in synchronization with a clock signal. The number of stages of latch circuits between the read register group and the data output terminal 4 is reduced by one stage, the transmission of data from the read register group 20 up to the latch circuit 30 and the transmission of data from the latch circuit 30 up to a data register are performed at a high speed without being subjected to the influence of a gate propagation delay, and it is possible to obtain the synchronous semiconductor memory device in which data can be read at a high speed and which is operated at a high frequency.

公开(公告)号：JPH08180676A

公开(公告)日：1996-07-12

申请号：JP32069994

申请日：1994-12-22

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： ARAKI TAKESHI ,  IWAMOTO HISASHI

IPC: G11C11/407

Abstract: PURPOSE: To provide a synchronous semiconductor memory having an internal clock generating circuit capable of always obtaining an exact internal clock signal even when the operating frequency is fluctuated. CONSTITUTION: Inverters IG1-IG(N+M) as the main part of a ring oscillator in a voltage controlled oscillator of a PLL circuit in a SDRAM are connected in series, the output part of the inverter IGN is connected to a node N1, the output part of the inverter IG(N+M) is connected to a node N2 and the input part of the inverter IG1 is connected to a node N3. A switching circuit 2 makes either a path between nodes N1 and N3 or a path between nodes N2 and N3 a continuity state based on CAS latency information V1. Namely, when the CAS latency information V1 instructs comparatively large CAS latency, the path between nodes N1 and N3 is made to be a continuity state and when it instructs comparatively small CAS latency, the path between nodes N2 and N3 is made to be a continuity state.

公开(公告)号：JPH0836883A

公开(公告)日：1996-02-06

申请号：JP17507994

申请日：1994-07-27

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： WATANABE NAOYA ,  KONISHI YASUHIRO ,  IWAMOTO HISASHI

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407

Abstract: PURPOSE:To obtain a semiconductor memory being easy to use in which pre- charge timing does not disturb other commands. CONSTITUTION:When a mode set signal MS outputted from a mode set setting circuit 4 is a 'H' level, a pre-charge signal generating circuit 5 activates a pre-charge start signal for all banks other than the bank specified by a bank address signal out of pre-charge start signals P0-P7. Also, when a mode set signal MS is a 'L' level, a pre-charge signal generating circuit 5 activates only a pre-charge start signal corresponding to the bank specified by a bank address signal. Therefore, pre-charging only the prescribed bank or pre-chargeing simultaneously all other banks can be performed in accordance with the mode set signal MS.

公开(公告)号：JPH04252486A

公开(公告)日：1992-09-08

申请号：JP1767791

申请日：1991-02-08

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： KONISHI YASUHIRO ,  DOSAKA KATSUMI ,  HAYANO KOJI ,  KUMANOTANI MASAKI ,  YAMAZAKI AKIRA ,  IWAMOTO HISASHI

IPC: G11C11/409 ,  G11C11/00 ,  G11C11/401 ,  G11C11/407

Abstract: PURPOSE:To provide a semiconductor memory incorporating cache capable of applying to arbitrary mapping system with small chip area. CONSTITUTION:The semiconductor memory incorporating cache includes SRAM 2 as cashe memory and DRAM 1 as main memory. DRAM array and SRAM array 2 allow the end batch transfer for data block via a bi-directional transfer gate circuit 3, an internal data line SBL and 16a, 16b. In DRAM array 1, a DRAW low decoder 14 and a DRAW column decoder 15 are provided. In SRAM array 2, a SRAM low decoder 21 and a SRAM column decoder 22 are provided. Each address in these SRAM array 2 and DRAM array 1 is independently given.

公开(公告)号：JP2003304150A

公开(公告)日：2003-10-24

申请号：JP2002108046

申请日：2002-04-10

Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

Inventor： IWAMOTO HISASHI

IPC: G06F12/00 ,  G06F13/16 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory whose signal transferring speed is quickened.
SOLUTION: This SDRAM1 is provided with a comparator 24.1 for deciding whether or not the level of the output signal of an output buffer 43.1 is higher than a reference level VR in the calibration mode of the output buffer 43.1 of a memory controller 2, and for outputting a level signal indicating the decision result and an output buffer 23.0 for outputting the output signal of the comparator 24.1 through a data input/output terminal T0 to a memory controller 2. Therefore, the current driving force of the output buffer 43.1 of the memory controller 2 can be adjusted, and the data transferring speed can be quickened.
COPYRIGHT: (C)2004,JPO

Abstract translation: 解决的问题：提供信号传送速度加快的半导体存储器。 解决方案：该SDRAM1具有比较器24.1，用于在存储器控制器2的输出缓冲器43.1的校准模式下判定输出缓冲器43.1的输出信号的电平是否高于参考电平VR 并且用于输出指示判定结果的电平信号和用于通过数据输入/输出端T0将比较器24.1的输出信号输出到存储器控制器2的输出缓冲器23.0。因此，输出缓冲器43.1的当前驱动力 可以调节存储器控制器2，并且可以加快数据传送速度。 版权所有（C）2004，JPO