公开(公告)号：JP2003281889A

公开(公告)日：2003-10-03

申请号：JP2003029521

申请日：2003-02-06

Applicant: Mitsubishi Electric Corp ,  Mitsubishi Electric Engineering Co Ltd ,  三菱電機エンジニアリング株式会社 ,  三菱電機株式会社

Inventor： MURAI YASUMITSU ,  IWAMOTO HISASHI ,  KONISHI YASUHIRO ,  WATANABE NAOYA ,  SAWADA SEIJI

IPC: H01L27/04 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous semiconductor memory device being operated at high speed and stably without increasing chip area. SOLUTION: Internal potential generating circuits (1914 and 1916) generating internal potentials conforming to charge pump operation corresponding to each of banks are arranged. For this internal potential generating circuits, a switch circuit (1912) receiving bank address signals (BAA, BAB) specifying a bank and a clock signal and transmitting a clock signal to a selected bank as a clock signal for driving the charge pump are arranged. Internal potentials can be generated with the bank unit and internal potentials can be supplied stably to a selected bank. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供在不增加芯片面积的情况下高速且稳定地操作的同步半导体存储器件。

解决方案：布置产生符合与每个组相对应的电荷泵操作的内部电位的内部电位发生电路（1914和1916）。 对于该内部电位产生电路，设置接收指定存储体和时钟信号的存储体地址信号（BAA，BAB）并将时钟信号发送到所选存储体的开关电路（1912）作为用于驱动电荷泵的时钟信号。 内部电位可以通过存储单元生成，内部电位可以稳定地提供给选定的存储区。 版权所有（C）2004，JPO

公开(公告)号：JP2002015573A

公开(公告)日：2002-01-18

申请号：JP2000198654

申请日：2000-06-30

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： KONISHI YASUHIRO

IPC: G11C11/407 ,  G11C5/14

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which no through-current flows in a deactivated circuit. SOLUTION: A common circuit 1 includes deactivating/activating circuits 10 and 20. Dedicated circuits 2 and 3 include inverters IV3, IV4, IV5 and IV6 in an input part. When an SDR-SDRAM is produced, the circuit 10 outputs a deactivating signal DASL, which is fixed to a ground potential to the circuit 3 and the circuit 20 outputs signals /OE, which are generated by inverting output enable signals OE into the circuit 2. Then, the intervals IV5 and IV6 of the circuit 2 output signals based on the signals /OE. Furthermore, an N-channel MOS transistor 31 and a P-channel MOS transistor 35 of the circuit 3 are turned off completely, and on through-current flows from power supply nodes 33 to ground terminals 34 in the circuit 3.

公开(公告)号：JP2001273766A

公开(公告)日：2001-10-05

申请号：JP2001056850

申请日：2001-03-01

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： KONISHI YASUHIRO ,  DOSAKA KATSUMI ,  HAYANO KOJI ,  KUMANOTANI MASAKI ,  YAMAZAKI AKIRA ,  IWAMOTO HISASHI

IPC: G11C11/41 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To change a data output mode in accordance with use environment. SOLUTION: An output control circuit (272b) sets the data output timing of an output circuit (274a) conforming to an output mode specifying signal stored in a command register (270).

公开(公告)号：JP2001101860A

公开(公告)日：2001-04-13

申请号：JP27376999

申请日：1999-09-28

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： AMANO TERUHIKO ,  FURUYA KIYOHIRO ,  HAMAMOTO TAKESHI ,  KONISHI YASUHIRO ,  KONO TAKASHI

IPC: G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To easily realize a synchronous semiconductor memory operating in operation modes of a single data rate and a double data rate while using a common chip. SOLUTION: A memory array is divided into two memory cell mats (4a, 4b) and when this memory operates in the operation mode of the single data rate, these cell mats are respectively used as an upper-order bit data storage area and a lower-order bit data storage area and when the memory operates in the operation mode of the double data rate, they are respectively used as an even numbered column address data storage area and an odd numbered column address data storage area.

公开(公告)号：JP2001067866A

公开(公告)日：2001-03-16

申请号：JP24259799

申请日：1999-08-30

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： FURUYA KIYOHIRO ,  KONISHI YASUHIRO

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To obtain a synchronous semiconductor storage for fully rewriting data to a memory cell when reading/writing the data. SOLUTION: In an SDRAM, a signal ZS0D reaching a low activation level in specific time Td after a sense amplifier activation signal SON reaches a high activation level is introduced. When a signal COLP reaching the high level during a burst period becomes a low level and the signal ZS0D reaches a low level, a word line WL is lower to a low non-selection level, thus fully amplifying the potential difference between a pair of bit lines BL and /BL and fully rewriting data to a memory cell MC.

公开(公告)号：JPH10283779A

公开(公告)日：1998-10-23

申请号：JP9078797

申请日：1997-04-09

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI ,  KONISHI YASUHIRO

IPC: G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To surely write and read data at a high operational frequency by increasing a wiring time within the range of latency according to the writing operational frequency of the data and by securing a writing period. SOLUTION: As shown by an external clock signal ext. CLK, figures A and B indicate that an operational frequency is set to a relatively low value and a relatively high value, respectively. When the operational frequency is set to the relatively high value (approximately 100 MHz under current situation), the completion of the writing operation of two-bit data is delayed by a specific time, More specifically, a CAS latency is set to a large value according to the increment of the operational frequency and a reading timing is eased, thus utilizing one portion of the reading operation time as a writing time, and hence expanding a writing margin, and securing a writing time.

公开(公告)号：JPH09223389A

公开(公告)日：1997-08-26

申请号：JP2785496

申请日：1996-02-15

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI ,  KONISHI YASUHIRO

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/408

Abstract: PROBLEM TO BE SOLVED: To provide a SDRAM(synchronous dynamic random access memory) which allows the changeover of pit configuration and is of a small area penalty. SOLUTION: A selector 116a is installed so that in the X8 configuration mode, two-bit serial data signals from an input/output terminal 112 on one side are supplied to two input/output line pairs, as parallel data signals 121a, 122a, and in the X16 configuration mode, two-bit parallel data signals from the data input/output terminals 112, 113 on both sides are directly supplied to two input/output line pairs 121a, 122a. By this, the X8 configuration mode and the X16 configuration mode give two-bit prefetch system and a single pipeline system respectively.

公开(公告)号：JPH08293789A

公开(公告)日：1996-11-05

申请号：JP9840695

申请日：1995-04-24

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： ARAKI TAKESHI ,  IWAMOTO HISASHI ,  KONISHI YASUHIRO

IPC: H03L7/081

Abstract: PURPOSE: To provide an internal clock signal generation circuit by which a correct internal clock signal can be obtained even in the case where an external clock signal is of small amplitude. CONSTITUTION: In the internal clock signal generation circuit (PLL, etc.), it is constituted so as to be provided with an amplitude converting means 10 which converts the internal clock signal into the internal clock signal of the amplitude similar to the external clock signal, and inputs that converted internal clock signal to a phase comparing means 100. By converting the internal clock signal into the internal clock signal of the small amplitude similar to the external clock signal, the internal clock signal locked exactly to the external clock signal can be obtained.

公开(公告)号：JPH08106778A

公开(公告)日：1996-04-23

申请号：JP24002294

申请日：1994-10-04

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： IWAMOTO HISASHI ,  KONISHI YASUHIRO ,  ARAKI TAKESHI

IPC: G11C11/407 ,  G11C11/401

Abstract: PURPOSE: To obtain a synchronous semiconductor memory operatable at high speeds and having an excellent randomness. CONSTITUTION: An internal clock signal is generated by an internal clock generation circuit 80 in synchronizm with an external clock signal, and an internal address and an external control signal are taken in synchronizm with the internal clock signal to set a mode with a mode setting circuit 83. Then, when the mode is judged to be the writing mode by an operation judging circuit 84, the internal clock signal is counted by a clock counter 86 and a mode switching signal is generated to determine whether a data is written into a memory cell bit by bit or by the several bits based on the mode signal and a counting output obtained.

公开(公告)号：JPH0676567A

公开(公告)日：1994-03-18

申请号：JP8459193

申请日：1993-04-12

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： KONISHI YASUHIRO ,  MIYAMOTO TAKAYUKI ,  KAJIMOTO TAKESHI ,  IWAMOTO HISASHI

IPC: G06F12/06 ,  G06F12/00 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/41 ,  G11C11/413 ,  H01L21/8242 ,  H01L27/108

Abstract: PURPOSE:To provide a multifunctional synchronism type semiconductor memory device which is small in a chip area, fast, and low in power consumption. CONSTITUTION:Memory arrays 6a and 6b are divided into banks which can independently operate and the respective banks #1 and #2 are provided with registers 10a and 10b for read data storage and registers 16a and 16b for write data storage which independently operate. The memory arrays are divided into small array blocks, and local IO lines are arranged corresponding to the respective array blocks and connected to a global IO line, which is connected to a preamplifier groups 8a and 8b and write buffer groups 14a and 14b. Control signal generating circuits 20 and 22 and a register control circuit 28 delay the timing of the writing inhibition of only a desired bit at the time of continuous writing operation, batch writing to a selected memory cell at the point of time of final data input when data writing is interrupted with less than lap length in the successive writing, and the activation of the memory array when a write cycle is repeatedly executed.