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    Method and circuit arrangement for reading out and for storing binary memory cell signals
    2.
    发明授权
    Method and circuit arrangement for reading out and for storing binary memory cell signals 失效
    用于读出和存储二进制存储单元信号的方法和电路装置

    公开(公告)号：US06721219B2

    公开(公告)日：2004-04-13

    申请号：US10150340

    申请日：2002-05-17

    申请人： Athanasia Chrysostomides ,  Sabine Kling ,  Peter Pfefferl ,  Dominique Savignac ,  Helmut Schneider

    发明人： Athanasia Chrysostomides ,  Sabine Kling ,  Peter Pfefferl ,  Dominique Savignac ,  Helmut Schneider

    IPC分类号： G11C700

    CPC分类号： G11C7/065 ,  G11C2207/002

    摘要： The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.

    摘要翻译： 本发明提供一种方法，其中来自a的二进制存储单元信号， 至少一个存储单元被施加到至少一个位线对（201t，201b），来自存储器的二进制存储器单元信号经由位线对（201t，201b）被切换到至少一个读出放大器（202） 将读出放大器（202）的二进制输出信号作为二进制中间信号切换到本地数据线对（205），将本地数据线对（205）上的二进制中间信号切换到至少一个 主数据线开关晶体管对（209）以主数据线切换晶体管对（209）的方式依赖于通过行控制线（210）馈送的行控制信号，主数据线开关晶体管对（209） 布置在形成在存储单元阵列之间的贯通电镀区域中。

    Method for reading and storing binary memory cells signals and circuit arrangement
    5.
    发明授权
    Method for reading and storing binary memory cells signals and circuit arrangement 有权
    读取和存储二进制存储单元信号和电路布置的方法

    公开(公告)号：US06654271B2

    公开(公告)日：2003-11-25

    申请号：US10152950

    申请日：2002-05-21

    申请人： Karl-Peter Pfefferl ,  Athanasia Chrysostomides ,  Dominique Savignac

    发明人： Karl-Peter Pfefferl ,  Athanasia Chrysostomides ,  Dominique Savignac

    IPC分类号： G11C502

    CPC分类号： G11C7/18 ,  G11C7/10 ,  G11C2207/002

    摘要： The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

    摘要翻译： 本发明的特征在于一种用于读取和存储二进制存储单元信号的方法，其中一个存储单元和输出端之间的二进制存储单元信号的信号传输时间减少。 该方法包括将二进制存储单元信号应用于位线对; 通过读出放大器将来自位线对的二进制存储单元信号切换到本地数据线对; 通过主数据交换单元从本地数据线切换到主数据线对的放大的二进制存储单元信号; 以及经由第一主数据线和第二主数据线对输出经放大的二进制存储单元信号。

    Integrated DRAM memory component
    6.
    发明授权
    Integrated DRAM memory component 失效
    集成DRAM存储器组件

    公开(公告)号：US06771527B2

    公开(公告)日：2004-08-03

    申请号：US10650818

    申请日：2003-08-28

    申请人： Helmut Fischer ,  Athanasia Chrysostomides ,  Kazimierz Szczypinski

    发明人： Helmut Fischer ,  Athanasia Chrysostomides ,  Kazimierz Szczypinski

    IPC分类号： G11C506

    CPC分类号： G11C11/4097 ,  H01L27/10897

    摘要： An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.

    摘要翻译： 集成DRAM存储器组件具有读出放大器，其分别在集成部件的框架内由从单元阵列规则排列的多个晶体管结构以及具有用于位线信号放大的放大晶体管的信号互连结构形成。 放大晶体管具有相同的设计，并且它们在相邻的晶体管行中成对地相对置。 与晶体管行相关联并与其并行延伸的信号互连提供致动信号。 用于致动信号的信号互连具有与放大晶体管相同的布置对称性，这意味着相邻晶体管行中的放大晶体管处于相同的信号互连接近。

    Integrated DRAM memory module
    7.
    发明授权
    Integrated DRAM memory module 有权

    公开(公告)号：US06542395B2

    公开(公告)日：2003-04-01

    申请号：US10082553

    申请日：2002-02-25

    申请人： Athanasia Chrysostomides ,  Helmut Fischer

    发明人： Athanasia Chrysostomides ,  Helmut Fischer

    IPC分类号： G11C506

    CPC分类号： H01L27/10897 ,  H01L27/0207

    摘要： The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are arranged regularly in cell arrays and include amplification transistors for bit line signal amplification. The amplification transistors lie opposite one another in pairs, are structurally identical, and are arranged equally spaced apart in rows. Voltage equalization transistors ensure voltage equalization between sense amplifier drive signals. The cell array order provides for each row with amplification transistors situated in a structurally identical transistor environment to be interrupted in a predetermined period by voltage equalization transistors. The structure of the voltage equalization transistors in a region of proximity to the adjoining amplification transistors is adapted to the structure thereof, and the voltage equalization transistors are at the same distance from the mutually adjoining amplification transistors as the amplification transistors of the same row are from one another.