公开(公告)号：US6078534A

公开(公告)日：2000-06-20

申请号：US937570

申请日：1997-09-25

申请人： Karl-Peter Pfefferl ,  Martin Gall

发明人： Karl-Peter Pfefferl ,  Martin Gall

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/789 ,  G11C29/80

摘要： A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time. With such an arrangement, because the electronically erasable read-only-memory cell is electronically programmable, a defective normal memory cell may be replaced with a redundant memory cell the memory is packaged.

摘要翻译： 具有存储器单元阵列的存储器。 阵列包括多个正常存储器单元和冗余存储单元。 提供了一种解码器，用于响应于地址和正常条件信号选择正常存储器单元中的寻址的一个，并响应于该地址和故障状态信号对该冗余存储器单元进行了适配地址。 提供了具有电可擦除只读存储器单元的冗余解码器。 当这种只读存储器单元被编程到故障状态时，冗余解码器适于产生正常条件信号并将正常条件信号转换成故障条件信号。 只读存储器单元中的每一个包括快闪存储器单元，铁电存储器单元或其他这种类型的电可擦除只读存储器单元，其基本上是非易失性的并且能够将其编程状态保持相对较长 一段的时间。 通过这样的布置，由于电子可擦除只读存储器单元是可电子编程的，所以可以用存储器封装的冗余存储器单元替换有缺陷的正常存储单元。

公开(公告)号：US06654271B2

公开(公告)日：2003-11-25

申请号：US10152950

申请日：2002-05-21

申请人： Karl-Peter Pfefferl ,  Athanasia Chrysostomides ,  Dominique Savignac

发明人： Karl-Peter Pfefferl ,  Athanasia Chrysostomides ,  Dominique Savignac

IPC分类号： G11C502

CPC分类号： G11C7/18 ,  G11C7/10 ,  G11C2207/002

摘要： The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

摘要翻译： 本发明的特征在于一种用于读取和存储二进制存储单元信号的方法，其中一个存储单元和输出端之间的二进制存储单元信号的信号传输时间减少。 该方法包括将二进制存储单元信号应用于位线对; 通过读出放大器将来自位线对的二进制存储单元信号切换到本地数据线对; 通过主数据交换单元从本地数据线切换到主数据线对的放大的二进制存储单元信号; 以及经由第一主数据线和第二主数据线对输出经放大的二进制存储单元信号。

公开(公告)号：US06310793B1

公开(公告)日：2001-10-30

申请号：US09663583

申请日：2000-09-18

申请人： Martin Brox ,  Karl-Peter Pfefferl

发明人： Martin Brox ,  Karl-Peter Pfefferl

IPC分类号： G11C502

CPC分类号： G11C8/12 ,  G11C8/14

摘要： The segmented word line architecture has two master word lines, to which sub-word lines are alternately allocated. Two memory banks can thus be alternately assigned to the sub-word lines.

摘要翻译： 分段字线架构具有两条主字线，子字线被交替分配。 因此，可以将两个存储体交替地分配给子字线。

公开(公告)号：US20070262791A1

公开(公告)日：2007-11-15

申请号：US11739776

申请日：2007-04-25

申请人： Karl-Peter Pfefferl

发明人： Karl-Peter Pfefferl

IPC分类号： H03K19/0175

CPC分类号： G11C17/16 ,  G11C29/789

摘要： An integrated circuit includes a programmable circuit with a programmable element, and a storage circuit to store a storage state depending on a programming state of the programmable element of the programmable circuit unit. The storage circuit includes a first inverter circuit and a second inverter circuit. The strengthening and weakening of transistors of the first inverter circuit and of transistors of the second inverter circuit and also the repeated evaluation of the programming state of the programmable element enable the storage state stored in the storage circuit to be made resistant to corruption on account of alpha-particles or neutrons.

摘要翻译： 集成电路包括具有可编程元件的可编程电路，以及存储电路，用于根据可编程电路单元的可编程元件的编程状态来存储存储状态。 存储电路包括第一反相器电路和第二反相器电路。 第一逆变器电路和第二逆变器电路的晶体管的晶体管的强化和弱化以及可编程元件的编程状态的重复评估使得能够使存储在存储电路中的存储状态由于 α粒子或中子。

公开(公告)号：US06560134B2

公开(公告)日：2003-05-06

申请号：US10014776

申请日：2001-11-07

申请人： Martin Brox ,  Karl-Peter Pfefferl ,  Helmut Schneider ,  Robert Kaiser ,  Dominique Savignac

发明人： Martin Brox ,  Karl-Peter Pfefferl ,  Helmut Schneider ,  Robert Kaiser ,  Dominique Savignac

IPC分类号： G11C502

CPC分类号： G11C5/025 ,  H01L23/50 ,  H01L24/02 ,  H01L27/10805 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082

摘要： A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

公开(公告)号：US06295236B1

公开(公告)日：2001-09-25

申请号：US09553128

申请日：2000-04-19

申请人： Martin Brox ,  Karl-Peter Pfefferl

发明人： Martin Brox ,  Karl-Peter Pfefferl

IPC分类号： G11C700

CPC分类号： G11C29/70

摘要： The semiconductor memory of the random access type has data lines, which can be connected to the local data lines in the memory cell array. The data lines are combined in groups and at least one group or individual data lines of the groups are formed by redundant data lines. Input/output lines lead from the memory in groups. A bus system organized in two planes is provided. The first plane is provided with bus lines which can be connected to all of the input/output lines, on the one hand, and to all of the data lines, on the other hand. The second plane has a plurality of individual partial buses, whose bus lines can be connected to in each case all of the data lines of at least two groups of data lines, on the one hand, and to all of the input/output lines of in each case one group, on the other hand.

摘要翻译： 随机存取类型的半导体存储器具有可连接到存储单元阵列中的本地数据线的数据线。 数据线被组合成组，且组中的至少一个组或各个数据线由冗余数据线形成。 输入/输出线从组中的内存引出。 提供组织在两个飞机上的总线系统。 另一方面，第一平面设置有可以连接到所有输入/输出线路以及所有数据线路的总线。 第二平面具有多个单独的部分总线，其总线可以在每种情况下连接至少两组数据线的所有数据线，一方面连接到所有输入/输出线 另一方面，在每种情况下都是一组。

公开(公告)号：US06226219B1

公开(公告)日：2001-05-01

申请号：US09549275

申请日：2000-04-14

申请人： Thoai-Thai Le ,  Andrea Trunk ,  Karl-Peter Pfefferl

发明人： Thoai-Thai Le ,  Andrea Trunk ,  Karl-Peter Pfefferl

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C8/10 ,  G11C8/12

摘要： The memory banks of semiconductor memories are activated via memory bank decoders. Two groups of memory banks are actuated via identical memory bank decoders. A predecoder is used to switch between the memory bank decoders. The layout of a memory bank decoder in a memory with a smaller memory capacity can thus be transferred without a change to a memory with a greater memory capacity.

摘要翻译： 半导体存储器的存储体通过存储体解码器被激活。 通过相同的存储体解码器来驱动两组存储体。 预解码器用于在存储体解码器之间切换。 因此，具有较小存储器容量的存储器存储器解码器的布局可以被转移而不改变具有更大存储容量的存储器。

公开(公告)号：US5978931A

公开(公告)日：1999-11-02

申请号：US895061

申请日：1997-07-16

申请人： Toshiaki Kirihata ,  Garbiel Daniel ,  Jean-Marc Dortu ,  Karl-Peter Pfefferl

发明人： Toshiaki Kirihata ,  Garbiel Daniel ,  Jean-Marc Dortu ,  Karl-Peter Pfefferl

IPC分类号： G11C29/44 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/804 ,  G11C29/808

摘要： A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

摘要翻译： 描述了具有可变域冗余替换（VDRR）布置的容错存储器件。 存储器件包括：多个主存储器阵列; 多个域具有与另一域共同的一个域的至少部分以形成重叠域区域，并且至少一个域重叠至少两个主存储器阵列的部分; 冗余单元，耦合到每个域，用于替换每个域内包含的故障; 控制电路，用于将要被所述冗余单元替换的所述域内的至少一个故障引导到所述冗余单元，其中所述一个域的至少一个其它故障被耦合到所述域中的另一个的所述冗余单元替换，如果至少 另一个故障位于重叠域区域内。 支持主存储器阵列的每个冗余单元包括多个冗余元件。 与传统的固定域冗余替换方案不同，RU被分配给至少两个可变域，其中域的至少一部分与另一个域的共同。 VDRR使得可以选择最有效的域，特别是用于修复随机故障的较小域或用于修复集群故障的较大域。

公开(公告)号：US06721219B2

公开(公告)日：2004-04-13

申请号：US10150340

申请日：2002-05-17

申请人： Athanasia Chrysostomides ,  Sabine Kling ,  Peter Pfefferl ,  Dominique Savignac ,  Helmut Schneider

发明人： Athanasia Chrysostomides ,  Sabine Kling ,  Peter Pfefferl ,  Dominique Savignac ,  Helmut Schneider

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C2207/002

摘要： The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.

摘要翻译： 本发明提供一种方法，其中来自a的二进制存储单元信号， 至少一个存储单元被施加到至少一个位线对（201t，201b），来自存储器的二进制存储器单元信号经由位线对（201t，201b）被切换到至少一个读出放大器（202） 将读出放大器（202）的二进制输出信号作为二进制中间信号切换到本地数据线对（205），将本地数据线对（205）上的二进制中间信号切换到至少一个 主数据线开关晶体管对（209）以主数据线切换晶体管对（209）的方式依赖于通过行控制线（210）馈送的行控制信号，主数据线开关晶体管对（209） 布置在形成在存储单元阵列之间的贯通电镀区域中。

公开(公告)号：US6138214A

公开(公告)日：2000-10-24

申请号：US994829

申请日：1997-12-19

申请人： Karl Peter Pfefferl

发明人： Karl Peter Pfefferl

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G06F12/00

CPC分类号： G11C8/04 ,  G11C7/1018 ,  G11C7/1072

摘要： An electronic memory device which includes a memory array having a plurality of memory cells arranged into a plurality of units. Each unit is divided into a first portion including only even addressed memory cells and a second portion including only odd addressed memory cells. A column decoder and row decoder are coupled to the memory array for selecting a number of the plurality of memory cells. A sense amplifier is coupled to the memory array for performing read and write operations from the selected memory cells. An address line is split for application of a split address to said even and odd addressed memory cells.

摘要翻译： 一种电子存储装置，包括具有布置成多个单元的多个存储单元的存储器阵列。 每个单元被分成仅包括偶数寻址的存储器单元的第一部分和仅包括奇数寻址的存储器单元的第二部分。 列解码器和行解码器耦合到存储器阵列，用于选择多个存储单元的数目。 感测放大器耦合到存储器阵列，用于从所选择的存储器单元执行读和写操作。 分割地址线以将分割地址应用于所述偶数和奇数寻址的存储单元。