公开(公告)号：US20120016502A1

公开(公告)日：2012-01-19

申请号：US13191208

申请日：2011-07-26

Applicant: Sridhar G. Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

Inventor： Sridhar G. Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

IPC: G06F17/00

CPC classification number: G06F15/167 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3877 ,  G06F9/3897

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract translation: 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。

公开(公告)号：US08589634B2

公开(公告)日：2013-11-19

申请号：US13481229

申请日：2012-05-25

Applicant: Sridhar G. Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

Inventor： Sridhar G. Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

IPC: G06F12/00

CPC classification number: G06F15/167 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3877 ,  G06F9/3897

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract translation: 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。

公开(公告)号：US09536535B2

公开(公告)日：2017-01-03

申请号：US13977640

申请日：2012-03-30

Applicant: Dongsheng Bi ,  Binuraj Ravindran ,  Bassel Haddad

Inventor： Dongsheng Bi ,  Binuraj Ravindran ,  Bassel Haddad

IPC: H04L27/06 ,  G10L19/16 ,  H04N7/24 ,  H04N21/438 ,  H04H20/42 ,  H04N21/443

CPC classification number: G10L19/167 ,  H04H20/426 ,  H04H2201/18 ,  H04N7/24 ,  H04N21/4382 ,  H04N21/4435 ,  H04N2007/246

Abstract: Described herein are systems, methods and apparatus for decoding in-band on-channel signals and extracting audio and data signals. Memory requirements are reduced by selectively filtering a bit stream of data in the signal so that services of interest which are encoded therein are processed. A single pool of memory may be shared between physical layer and data link layer processing. Memory in this pool may be allocated dynamically between processing of data at the physical and data link layers. When the available memory is not sufficient to support the required services, the dynamic allocation allows for graceful degradation.

Abstract translation: 这里描述了用于解码带内通道信号和提取音频和数据信号的系统，方法和装置。 通过选择性地过滤信号中的数据的比特流来减少存储器要求，从而处理其中编码的感兴趣的服务。 可以在物理层和数据链路层处理之间共享单个存储器池。 可以在物理层和数据链路层的数据处理之间动态地分配该池中的存储器。 当可用内存不足以支持所需的服务时，动态分配允许优雅的降级。

公开(公告)号：US20160284349A1

公开(公告)日：2016-09-29

申请号：US14670355

申请日：2015-03-26

Applicant: Binuraj Ravindran ,  Georg Stemmer ,  Joachim Hofer

Inventor： Binuraj Ravindran ,  Georg Stemmer ,  Joachim Hofer

IPC: G10L15/22 ,  G10L15/20 ,  G10L25/84 ,  G10L25/48 ,  G10L21/02 ,  G10L25/03

CPC classification number: G10L15/20 ,  G10L15/083 ,  G10L15/285 ,  G10L25/48 ,  G10L2015/226

Abstract: A system, article, and method of environment-sensitive automatic speech recognition.

Abstract translation: 环境敏感自动语音识别的系统，文章和方法。

公开(公告)号：US20120265329A1

公开(公告)日：2012-10-18

申请号：US13481229

申请日：2012-05-25

Applicant: Sridhar G. SHARMA ,  Binuraj RAVINDRAN ,  Jeffrey V. HILL

Inventor： Sridhar G. SHARMA ,  Binuraj RAVINDRAN ,  Jeffrey V. HILL

IPC: G06F17/00

CPC classification number: G06F15/167 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3877 ,  G06F9/3897

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

公开(公告)号：US20080263285A1

公开(公告)日：2008-10-23

申请号：US12148747

申请日：2008-04-21

Applicant: Sridhar Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

Inventor： Sridhar Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

IPC: G06F12/00 ,  G06F15/76 ,  G06F17/10 ,  G06F9/30

CPC classification number: G06F15/167 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3877 ,  G06F9/3897

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract translation: 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。

公开(公告)号：US08015368B2

公开(公告)日：2011-09-06

申请号：US12148747

申请日：2008-04-21

Applicant: Sridhar Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

Inventor： Sridhar Sharma ,  Binuraj Ravindran ,  Jeffrey V. Hill

IPC: G06F12/00

CPC classification number: G06F15/167 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3877 ,  G06F9/3897

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract translation: 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。