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公开(公告)号：US20120265329A1
公开(公告)日：2012-10-18
申请号：US13481229
申请日：2012-05-25
IPC分类号： G06F17/00
CPC分类号： G06F15/167 , G06F9/30014 , G06F9/3012 , G06F9/3877 , G06F9/3897
摘要： Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
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公开(公告)号：US20080263285A1
公开(公告)日：2008-10-23
申请号：US12148747
申请日：2008-04-21
CPC分类号： G06F15/167 , G06F9/30014 , G06F9/3012 , G06F9/3877 , G06F9/3897
摘要： Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
摘要翻译： 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。
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公开(公告)号：US06219775B1
公开(公告)日：2001-04-17
申请号：US09040747
申请日：1998-03-18
申请人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
发明人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
IPC分类号： G06F702
CPC分类号： G06F15/8092 , G06F15/17381 , G06F15/8084 , G06F21/52
摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.
摘要翻译： 大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。 该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。 每个处理节点包括用于在网络上传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。 节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。 节点处理器进一步通过接口控制网络上的数据传输。 辅助处理器连接到存储器模块和节点处理器。 响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。 响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。
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公开(公告)号：US5872987A
公开(公告)日：1999-02-16
申请号：US714635
申请日：1996-09-16
申请人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
发明人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
IPC分类号： G06F15/173 , G06F15/78 , G06F15/80 , G06F7/02
CPC分类号： G06F15/8092 , G06F15/17381 , G06F15/8084 , G06F21/52
摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.
摘要翻译： 大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。 该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。 每个处理节点包括用于从网络传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。 节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。 节点处理器进一步通过接口控制网络上的数据传输。 辅助处理器连接到存储器模块和节点处理器。 响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。 响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。
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公开(公告)号：US20120016502A1
公开(公告)日：2012-01-19
申请号：US13191208
申请日：2011-07-26
IPC分类号： G06F17/00
CPC分类号： G06F15/167 , G06F9/30014 , G06F9/3012 , G06F9/3877 , G06F9/3897
摘要： Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
摘要翻译： 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。
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6.发明授权Parallel computer system with physically separate tree networks for data and control messages 失效并行计算机系统，具有用于数据和控制消息的物理分离的树形网络
公开(公告)号：US5590283A
公开(公告)日：1996-12-31
申请号：US380854
申请日：1995-01-27
申请人： W. Daniel Hillis , David C. Douglas , Charles E. Leiserson , Bradley C. Kuszmaul , Mahesh N. Ganmukhi , Jeffrey V. Hill , Monica C. Wong-Chan
发明人： W. Daniel Hillis , David C. Douglas , Charles E. Leiserson , Bradley C. Kuszmaul , Mahesh N. Ganmukhi , Jeffrey V. Hill , Monica C. Wong-Chan
IPC分类号： G06F15/16 , G06F11/00 , G06F11/08 , G06F11/22 , G06F15/173 , G06F15/80 , G06F15/163
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.
摘要翻译： 数字计算机包括多个处理元件，通信路由器和控制网络。 每个处理单元执行与命令有关的数据处理操作，至少一些处理单元通过控制网络接收的消息中的命令进行数据处理操作。 每个处理元件还产生和接收数据传送消息，每个数据传送消息包括包含地址的地址部分，用于传送到由该地址识别的另一个处理元件。 处理元件中的至少一个进一步生成用于通过通信路由器传送的控制网络消息。 通信路由器包括以“胖树”形式互连的路由器节点，并且控制网络包括以树形式互连的控制网络节点，处理元件连接在相应通信路由器的叶节点处， 控制网络。
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7.发明授权Parallel computer system including request distribution network for distributing processing requests to selected sets of processors in parallel 失效并行计算机系统，其包括用于并行地将选择的处理器组分配处理请求的请求分发网络
公开(公告)号：US5388214A
公开(公告)日：1995-02-07
申请号：US183219
申请日：1994-01-14
申请人： Charles E. Leiserson , Robert C. Zak, Jr. , W. Daniel Hillis , Bradley C. Kuszmaul , Jeffrey V. Hill
发明人： Charles E. Leiserson , Robert C. Zak, Jr. , W. Daniel Hillis , Bradley C. Kuszmaul , Jeffrey V. Hill
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transfer to selected ones of the processing nodes as identified by associated request address information, and receives processed data in response, the request address information identifying selected ones of the processing nodes to receive a processing request in parallel. The request distribution network distributes the processing requests to the processing nodes and returns processed data to the control node. The network includes a plurality of request distribution nodes connected in a plurality of levels to form a tree-structure, including an upper root level and a lower leaf level. Each request distribution node is connected to receive processing requests from, and to couple processed data to, a parent, the parent of the request distribution node of the root level comprising the control node, and each request distribution node being further connected to couple processing requests to and receive processed data from, selected children, the children of the request distribution nodes of the leaf level comprising the processing nodes. Each request distribution node, in response to request address information received from its parent, identifies selected ones of its children and thereafter couples further request address information which it receives and processing requests in parallel to its children.
摘要翻译： 一种包括多个处理节点，控制节点和请求分发网络的计算机。 每个处理节点接收处理请求并响应处理的数据生成。 控制节点生成用于传送到由相关联的请求地址信息识别的所选处理节点的处理请求，并响应于接收处理的数据，请求地址信息识别处理节点中选择的一个并行接收处理请求。 请求分配网络将处理请求分配给处理节点，并将处理后的数据返回给控制节点。 网络包括以多个级别连接的多个请求分发节点，以形成包括上根级和下叶级的树结构。 每个请求分发节点被连接以接收处理的请求，并且将处理的数据耦合到父节点，包括控制节点的根级别的请求分发节点的父节点，并且每个请求分配节点进一步连接以耦合处理请求 从所选择的孩子接收和接收包括处理节点的叶级别的请求分发节点的子节点。 每个请求分发节点响应于从其父节点接收到的请求地址信息，识别其子节点中的所选择的一个，然后将其接收到的进一步的请求地址信息与其子节点并行处理请求。
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公开(公告)号：US5020081A
公开(公告)日：1991-05-28
申请号：US409251
申请日：1989-09-19
申请人： John D. Allen , Jeffrey V. Hill
发明人： John D. Allen , Jeffrey V. Hill
CPC分类号： H04L7/10 , H04J3/0602
摘要： A communication link interface having an assembly register which is loaded in response to a transmitter's clock rate and unloaded in response to a receiver's clock connected to the interface. The assembly register holds a series of data words received from the communication link. Logic gates or flip flops are provided to insure a time delay between loading the assembly register and unloading it.
摘要翻译： 一种通信链路接口，其具有装配寄存器，该组合寄存器响应于发射机的时钟速率而被加载，并且响应于连接到接口的接收机的时钟而被卸载。 装配寄存器保存从通信链路接收的一系列数据字。 提供逻辑门或触发器以确保加载组装寄存器和卸载之间的时间延迟。
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9.发明授权
公开(公告)号：US4910754A
公开(公告)日：1990-03-20
申请号：US252460
申请日：1988-09-30
申请人： John D. Allen , Jeffrey V. Hill
发明人： John D. Allen , Jeffrey V. Hill
CPC分类号： H04J3/0602 , H04L7/10 , H04L2007/045 , H04L7/048
摘要： An initialization or synchronization method in which at least a predetermined number of synchronization messages are sent out over a two-way communication line. The receipt of a synchronization message is awaited before terminating the transmission of synchronization message. After the transmission of synchronization messages has been terminated the receipt of a non-synchronization message will complete the synchronization process. However, certain conditions may cause synchronization to be restarted such as a predetermined number of consecutive error messages, failure to receive any message in a predetermined number of clock signals, receiving more than a predetermined number of synchronization signals, or a reset command.
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公开(公告)号：US08015368B2
公开(公告)日：2011-09-06
申请号：US12148747
申请日：2008-04-21
IPC分类号： G06F12/00
CPC分类号： G06F15/167 , G06F9/30014 , G06F9/3012 , G06F9/3877 , G06F9/3897
摘要： Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
摘要翻译： 描述了用于加速频谱带复制（SBR）处理的硬件架构（例如RISC处理器或DSP处理器）的增强。 在一些实施例中，指令扩展配置可重构处理器以加速SBR和其他音频处理。 除了指令扩展之外，执行单元（例如乘法和累加单元（MAC））可以并行操作以减少音频处理周期的数量。 可以通过使用配置为与执行单元一起工作并快速获取和存储源和目标操作数的源和目标单元来进一步增强性能。
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