公开(公告)号：US5761454A

公开(公告)日：1998-06-02

申请号：US703563

申请日：1996-08-27

Applicant: Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

Inventor： Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

IPC: G06F13/42 ,  G06F13/36

CPC classification number: G06F13/4226

Abstract: A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit. There is further included second circuit for determining whether the PCI slave is still able to complete the PCI-MEMORY transaction. Additionally, there is included third circuit for asserting an asynchronous handshake acknowledge signal to cancel the CPU-PCI transaction and removing the deadlock condition if the PCI slave is unable to complete the PCI-MEMORY transaction.

Abstract translation: 一种用于解决耦合到计算机系统的存储器，主机总线和PCI总线的桥式电路中的死锁状态的死锁检测和分辨率电路。 主机总线和PCI总线被配置为同时和异步地运行。 桥接电路包括主机主电路和耦合在主机总线和PCI总线之间的PCI从属电路，并配置为从耦合到PCI总线的外部PCI主机服务PCI-MEMORY指令。 桥接电路内的PCI主电路和主机从电路耦合在PCI总线和主机总线之间，并配置为从耦合到主机总线的CPU服务CPU-PCI事务。 当PCI-MEMORY事务随着CPU-PCI事务的发布而同时进行时，发生上述死锁条件。 死锁检测和分辨率电路包括用于向桥接电路的PCI从站断言异步握手信号的第一电路。 还包括用于确定PCI从站是否仍然能够完成PCI-MEMORY事务的第二电路。 另外，包括用于断言异步握手确认信号以消除CPU-PCI事务的第三电路，并且如果PCI从设备不能完成PCI-MEMORY事务，则消除死锁条件。

公开(公告)号：US6021473A

公开(公告)日：2000-02-01

申请号：US703677

申请日：1996-08-27

Applicant: Barry M. Davis ,  Nicholas J. Richardson ,  Brian N. Fall

Inventor： Barry M. Davis ,  Nicholas J. Richardson ,  Brian N. Fall

IPC: G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0835

Abstract: A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data items to a write buffer in a bridge circuit which are to be sent out on a device bus, such as a PCI bus. When the CPU writes a data item to the shared memory after writing a data item to the write buffer, a dirty bit is set for each location in the write buffer that stores a data item. When a bus device requests access to the shared memory, the dirty bits are checked. If the dirty bits are set, the bus device is denied access to the shared memory to maintain write coherency. When bus device access is denied, the bus device is informed to retry its request at a later time, and data items in the write buffer are flushed to devices on the bus. The write buffer is disabled after flushing the data items so that the CPU cannot write additional data items to the write buffer until the bus device has retried and accessed the shared memory.

Abstract translation: 一种用于在计算机系统中的CPU和总线设备数据事务中维持一致性的方法和装置。 CPU可以将数据项写入与总线设备共享的存储器，并且还可以将数据项写入要在诸如PCI总线的设备总线上发送的桥接电路中的写入缓冲器。 在将数据项写入写入缓冲区之后，CPU将数据项写入共享存储器时，会为存储数据项的写缓冲区中的每个位置设置脏位。 总线设备请求访问共享内存时，会检查脏位。 如果脏位被置位，则总线设备被拒绝访问共享存储器以保持写入一致性。 当总线设备访问被拒绝时，总线设备被通知以在稍后的时间重试其请求，并且写入缓冲器中的数据项被刷新到总线上的设备。 在刷新数据项后，禁止写入缓冲区，以便在总线设备重试并访问共享存储器之前，CPU不能将额外的数据项写入写入缓冲区。

公开(公告)号：US5475854A

公开(公告)日：1995-12-12

申请号：US187960

申请日：1994-01-28

Applicant: Joseph A. Thomsen ,  Franklyn H. Story ,  David R. Evoy ,  W. Henry Potts ,  Brian N. Fall ,  Hrushikesh Nalubola

Inventor： Joseph A. Thomsen ,  Franklyn H. Story ,  David R. Evoy ,  W. Henry Potts ,  Brian N. Fall ,  Hrushikesh Nalubola

IPC: G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/14

CPC classification number: G06F13/385 ,  G06F13/32 ,  G06F13/423

Abstract: A serial bus Input/Output (I/O) system has multiple I/O devices which are all connected in daisy-chain fashion on a serial bus. These I/O devices service peripherals that may generate different interrupt requests or DMA requests to the system controller. These requests are encoded, serialized and transmitted to the system controller on the serial bus, allowing the system controller to service a large number of interrupt requests and DMA requests via the serial bus with a very small number of external pins.

Abstract translation: 串行总线输入/输出（I / O）系统具有多个I / O设备，均以菊花链方式连接在串行总线上。 这些I / O设备服务可能会向系统控制器产生不同的中断请求或DMA请求的外围设备。 这些请求被编码，串行化并传输到串行总线上的系统控制器，允许系统控制器通过具有极少数量的外部引脚的串行总线来服务大量的中断请求和DMA请求。