公开(公告)号：US5475854A

公开(公告)日：1995-12-12

申请号：US187960

申请日：1994-01-28

申请人： Joseph A. Thomsen ,  Franklyn H. Story ,  David R. Evoy ,  W. Henry Potts ,  Brian N. Fall ,  Hrushikesh Nalubola

发明人： Joseph A. Thomsen ,  Franklyn H. Story ,  David R. Evoy ,  W. Henry Potts ,  Brian N. Fall ,  Hrushikesh Nalubola

IPC分类号： G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/14

CPC分类号： G06F13/385 ,  G06F13/32 ,  G06F13/423

摘要： A serial bus Input/Output (I/O) system has multiple I/O devices which are all connected in daisy-chain fashion on a serial bus. These I/O devices service peripherals that may generate different interrupt requests or DMA requests to the system controller. These requests are encoded, serialized and transmitted to the system controller on the serial bus, allowing the system controller to service a large number of interrupt requests and DMA requests via the serial bus with a very small number of external pins.

摘要翻译： 串行总线输入/输出（I / O）系统具有多个I / O设备，均以菊花链方式连接在串行总线上。 这些I / O设备服务可能会向系统控制器产生不同的中断请求或DMA请求的外围设备。 这些请求被编码，串行化并传输到串行总线上的系统控制器，允许系统控制器通过具有极少数量的外部引脚的串行总线来服务大量的中断请求和DMA请求。

公开(公告)号：US5524220A

公开(公告)日：1996-06-04

申请号：US298988

申请日：1994-08-31

申请人： Deepak Verma ,  W. Henry Potts

发明人： Deepak Verma ,  W. Henry Potts

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3834

摘要： A digital computer system including a memory subsystem thereof for increasing the throughput of the digital computer system is disclosed, comprising a central processing unit (CPU), a main memory, and a Look-ahead Instruction Prefetch Buffer (LIPB) external to the CPU for prefetching at least one portion of instruction code from the main memory each time the CPU initiates a request for instruction code from the main memory and for accelerating the submission of the portion of instruction code to said CPU means upon request by said CPU means without a memory system delay that is usually required when accessing a larger number of memory locations in the main memory each time the CPU initiates an instruction code request. An intelligent posted write buffer (IPWB) is also provided for temporarily storing in a first-in first-out (FIFO) configuration a portion of write-to-memory data generated by the CPU executing a write operation and for subsequently applying the portion of write-to-memory data to the main memory thereby eliminating a possible stall incurred by the CPU while waiting for the write operation to be completed.

摘要翻译： 公开了一种数字计算机系统，包括用于增加数字计算机系统的吞吐量的存储器子系统，其包括CPU外部的中央处理单元（CPU），主存储器和预读指令预取缓冲器（LIPB），用于 每当CPU从主存储器发起对指令代码的请求时，从主存储器中预取至少一部分指令代码，并且用于在没有存储器的情况下根据所述CPU装置的请求加速将指令代码部分提交给所述CPU装置 每当CPU启动指令代码请求时访问主存储器中较大数量的存储器位置时通常需要的系统延迟。 还提供了一种智能贴写式写缓冲器（IPWB），用于以先入先出（FIFO）配置临时存储执行写入操作的CPU生成的写入存储器数据的一部分，并且随后将 写入存储器数据到主存储器，从而消除CPU在等待写入操作完成时引起的可能的停顿。

公开(公告)号：US5136180A

公开(公告)日：1992-08-04

申请号：US655018

申请日：1991-02-12

申请人： Kenneth P. Caviasca ,  Tein-Yow Yu ,  Ned D. Garinger ,  Pratiksh Parikh ,  W. Henry Potts ,  James B. Nolan

发明人： Kenneth P. Caviasca ,  Tein-Yow Yu ,  Ned D. Garinger ,  Pratiksh Parikh ,  W. Henry Potts ,  James B. Nolan

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount. A selector, for example, a multiplexor, selects output from either the first frequency divider or the second frequency divider as the system clock signal. When the first oscillating signal is being used to generate the system clock, the second input may be used to control the selection of frequency dividers.

摘要翻译： 电路产生系统时钟信号。 在电路的第一输入端放置第一振荡信号。 在第二输入端，可以放置第二振荡信号。 时钟检测逻辑连接到第二个输入。 时钟感测逻辑检测第二振荡信号是否存在于第二输入端。 当第二输入端不存在第二振荡信号时，选择第一振荡信号来产生系统时钟。 当第二振荡信号存在于第二输入端时，第二振荡信号被选择用于产生系统时钟。 所选择的振荡信号被分频以产生系统时钟信号。 第一分频器将选择的振荡信号除以第一量。 并行地，第二分频器将所选择的振荡信号除以第二量。 选择器，例如，多路复用器，选择来自第一分频器或第二分频器的输出作为系统时钟信号。 当第一个振荡信号用于产生系统时钟时，第二个输入可用于控制分频器的选择。