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公开(公告)号：US08230289B2
公开(公告)日：2012-07-24
申请号：US12161674
申请日：2006-11-14
CPC分类号： G06F15/17 , H04L1/1877 , H04L1/1887
摘要： A data processor system includes a first data processor unit for transmitting data units to a second data processor unit and a retry buffer for temporarily storing transmitted data units. The second data processor unit receives the transmitted data and includes an error detector for detecting an error in the received data. When an error is detected, the first data processor unit is notified and a controller causes a data selector to select data from a retry buffer. The first data processor unit limits retransmission of a data unit to a predetermined maximum number of times irrespective of whether the data unit is correctly received or not. This allows for an undisturbed flow of streaming data with an increased reliability.
摘要翻译： 数据处理器系统包括用于将数据单元发送到第二数据处理器单元的第一数据处理器单元和用于临时存储发送数据单元的重试缓冲器。 第二数据处理器单元接收所发送的数据，并且包括用于检测接收到的数据中的错误的错误检测器。 当检测到错误时，通知第一数据处理器单元，并且控制器使数据选择器从重试缓冲器中选择数据。 第一数据处理器单元将数据单元的重传限制到预定的最大次数，而不管数据单元是否被正确接收。 这允许流量数据的流量不受干扰，并具有增加的可靠性。
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2.发明授权公开(公告)号：US08004922B2
公开(公告)日：2011-08-23
申请号：US12479517
申请日：2009-06-05
IPC分类号： G11C7/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A power island for a system-on-a-chip (SoC) includes a first segment, a second segment, and a supply line. The first segment includes a hardware device and operates the hardware device at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic and operates the scalable logic at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal (VDD) and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics.
摘要翻译： 用于片上系统（SoC）的功率岛包括第一段，第二段和供电线。 第一段包括硬件设备，并以指示至少第一电压的第一功率特性来操作硬件设备。 第二段包括可伸缩逻辑，并以指示至少第二电压的第二功率特性来操作可伸缩逻辑。 可伸缩逻辑的第二功率特性与硬件设备的第一功率特性不同。 电源线接收外部电源信号（VDD），并将外部电源信号引导到第一段和第二段。 第二段改变外部电源信号的至少一个功率特性，以根据第二功率特性来操作可伸缩逻辑。
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3.发明申请TRANSMISSION METHOD, TRANSMITTER AND DATA PROCESSING SYSTEM COMPRISING A TRANSMITTER 有权传输方法，包含发射机的发射机和数据处理系统公开(公告)号：US20100107008A1
公开(公告)日：2010-04-29
申请号：US12449442
申请日：2008-01-31
申请人： Andrei Radulescu , David R. Evoy
发明人： Andrei Radulescu , David R. Evoy
CPC分类号： H04L1/1877 , H04L1/1635 , H04L1/1642 , H04L1/1848
摘要： A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data already present in the retransmission buffer is overwritten, selecting the one or more oldest data frames in the retransmission buffer to be overwritten, in case an error is determined in the received data frame, communicating an error message to the transmitter of the data frame, which error message at least comprises an indication of the sequence number of the last correctly received data frame—upon receipt of such message and if available, retransmitting one or more data frames from the retransmission buffer having a sequence number higher than the sequence number communicated in the message.
摘要翻译： 描述了发送数据的方法，包括以下步骤：产生用于发送的数据帧，包括序列号和用户数据的数据帧，在重发缓冲器中保存数据帧的副本，以及如果所述保存步骤 复制要求重写缓冲区中已经存在的数据被覆盖，在接收到的数据帧中确定错误的情况下，选择要重写的重发缓冲器中的一个或多个最旧的数据帧，向错误消息传送错误消息 数据帧，该错误消息至少包括最后正确接收的数据帧的序列号的指示 - 在接收到这样的消息时，如果可用，则从具有高于序列的序列号的重发缓冲器重发一个或多个数据帧 消息中传达的号码。
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4.发明申请Simulation Circuit of Pci Express Endpoint and Downstream Port for a Pci Express Switch 有权Pci Express开关的Pci Express端点和下游端口的仿真电路公开(公告)号：US20080256284A1
公开(公告)日：2008-10-16
申请号：US10592191
申请日：2005-03-21
申请人： David R. Evoy , Jeremy Michael Rose
发明人： David R. Evoy , Jeremy Michael Rose
CPC分类号： G06F13/4022
摘要： Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement is adapted to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices.
摘要翻译： 呈现出两个看起来是分层的两个独立的硬件子系统的软件视图的单个硬件子系统是用PCI类型安排来实现的。 根据本发明的示例实施例，硬件布置适于在单个硬件块中模拟两个实际上分离的分层子系统。 这种仿真有助于将设备耦合到PCI Express型通信链路，同时解决这些设备的PCI-Express类型链接要求。
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5.发明授权公开(公告)号：US06766460B1
公开(公告)日：2004-07-20
申请号：US09645468
申请日：2000-08-23
申请人： David R. Evoy , Lonnie C. Goff , Bonnie Sexton
发明人： David R. Evoy , Lonnie C. Goff , Bonnie Sexton
IPC分类号： G06F128
CPC分类号： G06F9/3879 , G06F1/3203
摘要： A power management method is disclosed which provides power management for a hardware based Java accelerator. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.
摘要翻译： 公开了一种为基于硬件的Java加速器提供功率管理的功率管理方法。 最初，响应于启动Java应用程序，从主机处理器提供Java模式信号。 此后，减少了对主处理器的电力，并且响应于Java模式信号而增加了对Java处理器的供电。 然后，当Java应用程序的执行停止时，从Java处理器生成Java完成信号，从而发信号通知系统将控制返回到主机处理器。
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公开(公告)号：US06105142A
公开(公告)日：2000-08-15
申请号：US799099
申请日：1997-02-11
申请人： Lonnie C. Goff , David R. Evoy , Franklyn Story , Mark Sullivan
发明人： Lonnie C. Goff , David R. Evoy , Franklyn Story , Mark Sullivan
CPC分类号： G06F9/46 , G06F1/3203
摘要： A method and apparatus for managing power consumption in a computer system wherein the method and apparatus is compliant with the proposed Advanced Configuration and Power Interface (ACPI) specification. In one embodiment, a power management processor is sandwiched between platform hardware and the ACPI register layer. The processor processes all operating power management commands and requests while remaining transparent to the user and the operating system. In so doing, routine power management functions, so classified by the operating system, are implemented by the operating system. Sophisticated power management features, on the other hand, are implemented by the present invention independent from operating system control. Accordingly, in the present invention, the operating system need not suspend processing of other threads to process sophisticated power management procedures.
摘要翻译： 一种用于管理计算机系统中的功耗的方法和装置，其中所述方法和装置符合所提出的高级配置和电源接口（ACPI）规范。 在一个实施例中，电源管理处理器夹在平台硬件和ACPI寄存器层之间。 处理器处理所有操作电源管理命令和请求，同时对用户和操作系统保持透明。 这样做，由操作系统分类的日常电源管理功能由操作系统实现。 另一方面，复杂的电源管理功能由独立于操作系统控制的本发明实现。 因此，在本发明中，操作系统不需要暂停其他线程的处理来处理复杂的电源管理过程。
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7.发明授权System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status 失效用于通过硬件状态机在台式PC上实现外围设备总线主控制的系统，用于对DMA控制器进行编程，产生命令信号和接收完成状态
公开(公告)号：US5809333A
公开(公告)日：1998-09-15
申请号：US627988
申请日：1996-04-08
申请人： Franklyn H. Story , David R. Evoy , Peter Chambers , Lonnie Goff
发明人： Franklyn H. Story , David R. Evoy , Peter Chambers , Lonnie Goff
CPC分类号： G06F13/28
摘要： The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.
摘要翻译： 本发明是具有外围设备总线母盘的台式个人计算机（PC）系统。 该系统有四个主要元件：直接存储器访问（DMA）控制器，硬件状态机，总线控制器和设备控制器。 设备控制器可以是IDE硬盘控制器，其能够以间歇方式产生长数据流，其中任何单个数据流被定向到多个不同的主机存储器位置。 设备控制器还可以是ECP并行端口控制器，其通过并行总线与多个不同的外围设备进行接口，其中每个外围设备作为独立和独立的数据路径出现在系统中。
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8.发明授权Simulation circuit of PCI express endpoint and downstream port for a PCI express switch 有权PCI Express端口的模拟电路和PCI Express交换机的下行端口公开(公告)号：US07983888B2
公开(公告)日：2011-07-19
申请号：US10592191
申请日：2005-03-21
申请人： David R. Evoy , Jerry Michael Rose
发明人： David R. Evoy , Jerry Michael Rose
CPC分类号： G06F13/4022
摘要： Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI arrangements. In an embodiment, a hardware arrangement is configured to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express communications links while addressing PCI-Express linking requirements for such devices.
摘要翻译： 呈现出两个看起来是分层的两个独立的硬件子系统的软件视图的单个硬件子系统通过PCI安排来实现。 在一个实施例中，硬件布置被配置为在单个硬件块中模拟两个实际上分离的分层子系统。 这种仿真有助于将设备耦合到PCI Express通信链路，同时解决对这些设备的PCI-Express链接要求。
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9.发明申请AUTOMATIC CONFIGURATION OF A COMMUNICATION PORT AS TRANSMITTER OR RECEIVER DEPENDING ON THE SENSED TRANSFER DIRECTION OF A CONNECTED DEVICE 有权根据连接的设备的感应传输方向自动配置通信端口作为发送器或接收器公开(公告)号：US20090043931A1
公开(公告)日：2009-02-12
申请号：US10592190
申请日：2005-03-21
申请人： David R. Evoy , Dc Sessions , Dennis Koutsoures
发明人： David R. Evoy , Dc Sessions , Dennis Koutsoures
CPC分类号： G06F13/4072
摘要： A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.
摘要翻译： 实现通信端口用于配置方向和布置。 根据本发明的示例性实施例，诸如PCI Express类型链路的通信链路可配置为与具有不同方向和/或极性配置的设备进行通信。 通信链路被配置为匹配耦合到通信链路的设备的通信端口条件（例如，定向和/或极性条件）。 在一种情况下，通信链路是可定向配置的，用于重新分配输入通道以输出通道和输出通道到输入通道。 利用这种方法，通信链路可用于与具有不同通信特性的各种设备进行通信。
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公开(公告)号：US06839862B2
公开(公告)日：2005-01-04
申请号：US09871159
申请日：2001-05-31
CPC分类号： H04L7/0008 , H04L25/14
摘要： In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
摘要翻译： 在一个示例实施例中，高速并行数据通信方法通过包括多个并行数据携带线路和时钟路径的通信信道将数字数据从第一模块并行传送到第二模块。 并行总线布置成多个组，每个组包括多个数据传送线和适于承载时钟信号的时钟路径，用于将从第一模块承载的数字数据同步到第二模块。 使用并行总线的线路并行传送数据组，并且在第二模块处，并且对于每个组，经由该组的时钟信号同步地收集传送的数字数据。 在第二个模块中，对每个组收集的数据进行对齐。 通过将每个组具有自己的时钟域的组中的总线分组，通过在每个时钟域组内，然后在组之间首先处理数据和偏移来容忍和克服时钟域组之间的偏斜。
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