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公开(公告)号：US08153449B2
公开(公告)日：2012-04-10
申请号：US13113317
申请日：2011-05-23
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/1617 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.
摘要翻译： 一种用于封装半导体器件的方法。 该方法包括：在半导体器件上提供介电层; 确定材料在电介质层上的图案和放置以为器件提供预定的磁或电效应，这种效果仅通过耦合在这种材料和器件之间的电或磁波从这种图案化和放置的材料提供在器件上; 并以确定的图案和放置形成材料以提供预定的效果。
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公开(公告)号：US20100182092A1
公开(公告)日：2010-07-22
申请号：US12355865
申请日：2009-01-19
CPC分类号： H03H11/245
摘要： A variable attenuator having: an input port; a semiconductor device having a control electrode for controlling carriers flowing between a first electrode and a second electrode, such control electrode being coupled to one of the first and second electrodes, one of the first and second electrodes being coupled to the input port and the other one of the first and second electrodes being coupled to a reference potential to form an active device characterized by such device having a resistivity in the device to the flow of carriers substantially constant when such device is fed through input port with a signal having a relatively small power level and having a resistivity in the device to the flow of carriers which is nonlinear when such device is fed through input port with a signal having a relatively large power level; and an output port coupled to one of the first and second electrodes coupled to the input port. Such a network may be used with a power amplifier to reduce excessive small signal gain and soft compression.
摘要翻译： 一种可变衰减器，具有：输入端口; 具有用于控制在第一电极和第二电极之间流动的载流子的控制电极的半导体器件，所述控制电极耦合到第一和第二电极中的一个，第一和第二电极中的一个耦合到输入端口，另一个耦合到输入端口 所述第一和第二电极中的一个耦合到参考电位以形成有源器件，其特征在于，当所述器件通过输入端口馈送具有相对较小的信号时，所述器件具有器件中的电阻率与载流子基本上恒定的特性 功率电平并且当该装置通过具有相对大的功率电平的信号通过输入端口馈送时，该装置中的载流子电阻率是非线性的; 以及耦合到耦合到输入端口的第一和第二电极中的一个的输出端口。 这样的网络可以与功率放大器一起使用以减少过大的小信号增益和软压缩。
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3.发明授权公开(公告)号：US08963658B2
公开(公告)日：2015-02-24
申请号：US12886653
申请日：2010-09-21
IPC分类号： H01P5/08 , H01P5/02 , H01L29/812
CPC分类号： H01P5/028 , H01L29/812 , H01P5/08
摘要： A structure having a coplanar waveguide transistor; and a microwave section, coupled to the transistor, having: a strip conductor coplanar with the electrodes of the coplanar waveguide transistor and a ground plane conductor disposed under the strip conductor.
摘要翻译： 具有共面波导晶体管的结构; 以及耦合到所述晶体管的微波部分，具有：与所述共面波导晶体管的电极共面的带状导体，以及设置在所述带状导体下方的接地平面导体。
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4.发明授权Monolithic microwave integrated circuits (MMICs) having conductor-backed coplanar waveguides and method of designing such MMICs 有权具有导体背面共面波导的单片微波集成电路（MMIC）及其设计方法公开(公告)号：US08867226B2
公开(公告)日：2014-10-21
申请号：US13169521
申请日：2011-06-27
CPC分类号： H01L27/0629 , H01L27/0605 , H01Q5/371
摘要： A MMIC having: a substrate; a plurality of active and passive electrical elements disposed on a top surface of the substrate; a plurality of coplanar waveguide transmission line sections disposed on the top surface of the substrate for electrically interconnecting the active and passive electrical elements; an electrical conductor disposed on a bottom surface of the substrate under the coplanar waveguide section. Edges of ground plane conductors of the coplanar waveguide (CPW) sections have slots therein in regions thereof connected to the active and passive devices. The design of such circuit includes mathematical models of the CPW with the pair of local ground planes and the strip conductor thereof have relatively narrow connectable ports.
摘要翻译： 具有：底物的MMIC; 设置在所述基板的顶表面上的多个有源和无源电气元件; 多个共面波导传输线部分，设置在所述基板的顶表面上，用于将所述有源和无源电气元件电连接; 布置在共面波导部分下面的基板的底面上的电导体。 共面波导（CPW）部分的接地平面导体的边缘在其中连接到有源和无源器件的区域中具有槽。 这种电路的设计包括具有一对局部接地平面的CPW的数学模型，并且其带状导体具有相对窄的可连接端口。
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公开(公告)号：US07968978B2
公开(公告)日：2011-06-28
申请号：US12052158
申请日：2008-03-20
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/1617 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.
摘要翻译： 一种用于封装半导体器件的方法。 该方法包括：在半导体器件上提供介电层; 确定材料在电介质层上的图案和放置以为器件提供预定的磁或电效应，这种效果仅通过耦合在这种材料和器件之间的电或磁波从这种图案化和放置的材料提供在器件上; 并以确定的图案和放置形成材料以提供预定的效果。
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6.发明申请MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (MMICs) HAVING CONDUCTOR-BACKED COPLANAR WAVEGUIDES AND METHOD OF DESIGNING SUCH MMICs 有权具有导体背面共振波长的单片微波集成电路（MMIC）及其设计方法公开(公告)号：US20120327624A1
公开(公告)日：2012-12-27
申请号：US13169521
申请日：2011-06-27
IPC分类号： H05K7/00
CPC分类号： H01L27/0629 , H01L27/0605 , H01Q5/371
摘要： A MMIC having: a substrate; a plurality of active and passive electrical elements disposed on a top surface of the substrate; a plurality of coplanar waveguide transmission line sections disposed on the top surface of the substrate for electrically interconnecting the active and passive electrical elements; an electrical conductor disposed on a bottom surface of the substrate under the coplanar waveguide section. Edges of ground plane conductors of the coplanar waveguide (CPW) sections have slots therein in regions thereof connected to the active and passive devices. The design of such circuit includes mathematical models of the CPW with the pair of local ground planes and the strip conductor thereof have relatively narrow connectable ports.
摘要翻译： 具有：底物的MMIC; 设置在所述基板的顶表面上的多个有源和无源电气元件; 多个共面波导传输线部分，设置在所述基板的顶表面上，用于将所述有源和无源电气元件电连接; 布置在共面波导部分下面的基板的底面上的电导体。 共面波导（CPW）部分的接地平面导体的边缘在其中连接到有源和无源器件的区域中具有槽。 这种电路的设计包括具有一对局部接地平面的CPW的数学模型，并且其带状导体具有相对窄的可连接端口。
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7.发明申请公开(公告)号：US20120068793A1
公开(公告)日：2012-03-22
申请号：US12886653
申请日：2010-09-21
IPC分类号： H01P1/04
CPC分类号： H01P5/028 , H01L29/812 , H01P5/08
摘要： A structure having a coplanar waveguide transistor; and a microwave section, coupled to the transistor, having: a strip conductor coplanar with the electrodes of the coplanar waveguide transistor and a ground plane conductor disposed under the strip conductor.
摘要翻译： 具有共面波导晶体管的结构; 以及耦合到所述晶体管的微波部分，具有：与所述共面波导晶体管的电极共面的带状导体，以及设置在所述带状导体下方的接地平面导体。
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8.发明申请公开(公告)号：US20110223692A1
公开(公告)日：2011-09-15
申请号：US13113317
申请日：2011-05-23
IPC分类号： H01L21/02
CPC分类号： H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/1617 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.
摘要翻译： 一种用于封装半导体器件的方法。 该方法包括：在半导体器件上提供介电层; 确定材料在电介质层上的图案和放置以为器件提供预定的磁或电效应，这种效果仅通过耦合在这种材料和器件之间的电或磁波从这种图案化和放置的材料提供在器件上; 并以确定的图案和放置形成材料以提供预定的效果。
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9.发明申请公开(公告)号：US20080311682A1
公开(公告)日：2008-12-18
申请号：US12052158
申请日：2008-03-20
CPC分类号： H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/1617 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.
摘要翻译： 一种用于封装半导体器件的方法。 该方法包括：在半导体器件上提供介电层; 确定材料在电介质层上的图案和放置，以为器件提供预定的磁或电效应，这种效果仅通过耦合在这种材料和器件之间的电或磁波从这种图案化和放置的材料提供在器件上; 并以确定的图案和放置形成材料以提供预定的效果。
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