公开(公告)号：US20130228904A1

公开(公告)日：2013-09-05

申请号：US13673318

申请日：2012-11-09

Applicant: INTEL MOBILE COMMUNICATIONS GMBH

Inventor： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Brandl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract translation: 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

公开(公告)号：US08153449B2

公开(公告)日：2012-04-10

申请号：US13113317

申请日：2011-05-23

Applicant: Michael G. Adlerstein ,  Francois Y. Colomb

Inventor： Michael G. Adlerstein ,  Francois Y. Colomb

IPC: H01L21/00

CPC classification number: H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.

Abstract translation: 一种用于封装半导体器件的方法。 该方法包括：在半导体器件上提供介电层; 确定材料在电介质层上的图案和放置以为器件提供预定的磁或电效应，这种效果仅通过耦合在这种材料和器件之间的电或磁波从这种图案化和放置的材料提供在器件上; 并以确定的图案和放置形成材料以提供预定的效果。

公开(公告)号：US20090085808A1

公开(公告)日：2009-04-02

申请号：US11904986

申请日：2007-09-28

Applicant: Matthew R. Walsh ,  Deepukumar M. Nair ,  David W. Zimmerman ,  Benjamen E. Haffke ,  Scott D. Brandenburg ,  Charles I. Delheimer ,  Michael E. Miller ,  Bruce Wayne Butler

Inventor： Matthew R. Walsh ,  Deepukumar M. Nair ,  David W. Zimmerman ,  Benjamen E. Haffke ,  Scott D. Brandenburg ,  Charles I. Delheimer ,  Michael E. Miller ,  Bruce Wayne Butler

IPC: H01Q1/38

CPC classification number: H01L23/66 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2924/1617 ,  H01L2924/19032 ,  H01L2924/19039 ,  H01P5/107

Abstract: A microwave communication package is constructed on an electrically conducting base plate having a first side defining a base plate cavity, with an antenna apparatus mounted on an opposite, second side. A dielectric substrate on the first side of the base plate covers the base plate cavity; and sealing apparatus contacting the dielectric substrate and the base plate completely around the base plate cavity hermetically seals the cavity. Circuitry mounted on a surface of the substrate within the base plate cavity includes one or more microstrip lines communicating components to one or more waveguides comprising openings extending through the base plate; and the waveguides are coupled at their opposite ends to the antenna apparatus.

Abstract translation: 微波通信封装构造在具有限定基板空腔的第一侧的导电基板上，天线装置安装在相对的第二侧上。 基板的第一侧的电介质基板覆盖基板空腔; 并且密封装置使绝缘基板和基板完全围绕底板腔体密封，从而密封空腔。 安装在基板腔内的基板表面上的电路包括一个或多个微带线，其将部件传送到一个或多个包括穿过基板的开口的波导; 并且波导在其相对端耦合到天线装置。

公开(公告)号：US20080265421A1

公开(公告)日：2008-10-30

申请号：US11746936

申请日：2007-05-10

Applicant: Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger

Inventor： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger

IPC: H01L23/52 ,  H01L21/4763 ,  H01L23/552

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract translation: 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

公开(公告)号：US07109410B2

公开(公告)日：2006-09-19

申请号：US10825747

申请日：2004-04-15

Applicant: Rocky R. Arnold ,  John C. Zarganis ,  Fabrizio Montauti

Inventor： Rocky R. Arnold ,  John C. Zarganis ,  Fabrizio Montauti

IPC: H05K9/00

CPC classification number: H01L23/04 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/1617 ,  H01L2924/16315 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K9/003 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The present invention provides methods and devices for shielding an electronic component package. In one embodiment, an EMI shield is integrally formed within the package adjacent the die and grounded. The EMI shield may be a metallized shaped polymer layer and may be disposed fully within the package or it may extend out of the package.

Abstract translation: 本发明提供了用于屏蔽电子部件封装的方法和装置。 在一个实施例中，EMI屏蔽件在与封装件相邻的封装件内整体形成并接地。 EMI屏蔽可以是金属化形状的聚合物层，并且可以完全设置在封装内，或者它可以延伸出封装。

公开(公告)号：US20050036278A1

公开(公告)日：2005-02-17

申请号：US10932893

申请日：2004-09-02

Applicant: Kozo Murakami ,  Kunihiro Fujii ,  Satoshi Matsuo

Inventor： Kozo Murakami ,  Kunihiro Fujii ,  Satoshi Matsuo

IPC: H01L21/50 ,  H01L21/60 ,  H01L23/057 ,  H01L23/13 ,  H01L23/552 ,  H03H9/25 ,  H02B1/00

CPC classification number: H01L24/80 ,  H01L21/50 ,  H01L23/057 ,  H01L23/13 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/3025 ,  H03H9/1071 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package is provided with a stepped level-difference in the inner wall surface, and an internal contact electrode formed on the upper surface of the stepped level-difference. At the bottom of the package is a shield electrode, on which a chip is mounted via an adhesion layer. The chip and the internal contact electrode are electrically connected by an interconnection wire. Location aligning for the chip and the interconnection wire, at least either one of these, is conducted by making use of a region, which is non-electrode portion, provided on the inner bottom surface of the package.

Abstract translation: 一种电子部件，其中芯片可以以高精度水平安装在封装的某个预定位置，该封装在空腔的内壁中具有台阶级差。 该封装件在内壁表面上具有台阶级差，而形成在阶梯级差的上表面上的内部接触电极。 在封装的底部是屏蔽电极，其上通过粘合层安装芯片。 芯片和内部接触电极通过互连线电连接。 通过利用设置在封装的内底面上的非电极部分的区域来进行芯片和互连线的位置对准，其中至少任一个进行。

公开(公告)号：US06847115B2

公开(公告)日：2005-01-25

申请号：US09946553

申请日：2001-09-06

Applicant: Stanford W. Crane, Jr. ,  Myoung-Soo Jeon ,  Vicente D. Alcaria

Inventor： Stanford W. Crane, Jr. ,  Myoung-Soo Jeon ,  Vicente D. Alcaria

IPC: H01L23/057 ,  H01L23/498 ,  H01L23/552 ,  H05K9/00 ,  H01L29/04

CPC classification number: H01L24/32 ,  H01L23/057 ,  H01L23/49861 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.

Abstract translation: 一种封装半导体器件，其被制造成具有限定在条中的多个导电引线，其有利地包括射频屏蔽盒。 导电触点位于壳体中，有利地是通过插入成型或夹在底部件和顶部件之间。 壳体还可以包括容纳半导体器件的空腔，射频屏蔽可以接收另一个半导体器件。 接合导体将至少一个半导体器件电连接到另一个半导体器件和/或导电触点。 导电盖设置在壳体上。 空腔有利地包括斜面壁，并且导电引线和射频屏蔽有利地由铜组成。

公开(公告)号：US20040240191A1

公开(公告)日：2004-12-02

申请号：US10825999

申请日：2004-04-15

Applicant: Wavezero, Inc.

Inventor： Rocky R. Arnold ,  John C. Zarganis ,  Fabrizio Montauti

IPC: H01R004/26 ,  H01R011/20 ,  H01R004/24 ,  H05K007/14 ,  H05K007/18

CPC classification number: H01L23/04 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/1617 ,  H01L2924/16315 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K9/003 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The present invention provides shielded printed circuit boards and electronic devices. The printed circuit board may comprise an internal network of grounded conductive elements that are coupleable to an EMI shield that is mounted on the printed circuit board. The network of grounded conductive elements are coupleable to a grounded layer and to the EMI shield and provides improved EMI shielding through the volume of the printed circuit board below an electronic component mounted on the printed circuit board.

Abstract translation: 本发明提供屏蔽印刷电路板和电子设备。 印刷电路板可以包括可连接到安装在印刷电路板上的EMI屏蔽的接地导电元件的内部网络。 接地导电元件的网络可耦合到接地层和EMI屏蔽层，并通过安装在印刷电路板上的电子元件下面的印刷电路板的体积提供改进的EMI屏蔽。

公开(公告)号：US20040232536A1

公开(公告)日：2004-11-25

申请号：US10649731

申请日：2003-08-28

Inventor： Yoshiaki Fukuzumi

IPC: H01L021/44

CPC classification number: H01L23/552 ,  H01L23/057 ,  H01L23/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor chip provided with a magnetic element, and an enclosure which seals the magnetic chip. Substantially spherical magnetic substance particles are interspersed in the enclosure.

Abstract translation: 半导体器件包括设置有磁性元件的半导体芯片和密封该磁性芯片的外壳。 基本球形的磁性物质颗粒散布在外壳中。

公开(公告)号：US06635819B2

公开(公告)日：2003-10-21

申请号：US09825949

申请日：2001-04-04

Applicant: Yoshio Awakura ,  Koji Kamei ,  Satoshi Shiratori

Inventor： Yoshio Awakura ,  Koji Kamei ,  Satoshi Shiratori

IPC: H05K900

CPC classification number: H05K9/0049 ,  B82Y25/00 ,  H01F10/007 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/1617 ,  H01L2924/3011 ,  H05K9/0088 ,  Y10T428/12431 ,  H01L2924/00

Abstract: In an electronic component (11) comprising an electronic circuit or a circuit element in a metallic case including a case (13) and a cover (39), a magnetic thin film (51) made of a magnetic loss material is provided on at least one part of an inner wall surface of the metallic case. In the magnetic loss material, its composition is represented by M-X—Y, wherein M denotes at least one of Fe, Co and Ni, X denotes at least one of elements other than M and Y, and Y denotes at least one of F, N and O. The maximum value &mgr;″max of an imaginary part &mgr;″, which is an imaginary number component of a complex permeability of the magnetic loss material, exists within a frequency range from 100 MHz to 10 GHz. A relative bandwidth bwr is not greater than 200% where the relative bandwidth bwr is obtained by extracting a frequency bandwidth between two frequencies at which the value of &mgr;″ is 50% of the maximum &mgr;″max and normalizing the frequency bandwidth at the center frequency thereof. It is possible to provide an electronic component including a metallic case, which contains a high-speed operation type of semiconductor device and/or an electronic circuit and in which undesired radiation is reduced.

Abstract translation: 在包括壳体（13）和盖（39）的金属壳体中的电子电路或电路元件的电子部件（11）中，至少设置由磁损耗材料制成的磁性薄膜（51） 金属外壳的内壁表面的一部分。 在磁损耗材料中，其组成由MXY表示，其中M表示Fe，Co和Ni中的至少一种，X表示除M和Y以外的元素中的至少一种，Y表示F，N和 作为磁损耗材料的复磁导率的虚数分量的虚数μ“的最大值mu''max存在于从100MHz到10GHz的频率范围内。 相对带宽bwr不大于200％，其中通过提取两个频率之间的频率带宽获得相对带宽bwr，其中mu“的值是最大mu''max的50％，并且将频带宽度归一化 中心频率。 可以提供包括金属外壳的电子部件，其包含高速操作型半导体器件和/或电子电路，并且其中不期望的辐射被减少。