公开(公告)号：US20170084624A1

公开(公告)日：2017-03-23

申请号：US15245218

申请日：2016-08-24

申请人： CHANGHYUN LEE ,  HEONKYU LEE ,  SHINHWAN KANG ,  YOUNGWOO PARK

发明人： CHANGHYUN LEE ,  HEONKYU LEE ,  SHINHWAN KANG ,  YOUNGWOO PARK

IPC分类号： H01L27/115 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

公开(公告)号：US20180174661A1

公开(公告)日：2018-06-21

申请号：US15726002

申请日：2017-10-05

申请人： KWANG-SOO KIM ,  Heonkyu Lee

发明人： KWANG-SOO KIM ,  Heonkyu Lee

IPC分类号： G11C29/00 ,  G11C11/34

CPC分类号： G11C29/006 ,  G11C5/025 ,  G11C7/18 ,  G11C11/34 ,  G11C29/1201 ,  G11C29/48

摘要： A three-dimensional semiconductor memory device including a substrate including a first connection region, a second connection region, and a cell array region disposed between the first and second connection regions. The memory device further includes an electrode structure including a plurality of electrodes vertically stacked on the substrate, wherein each of the electrodes has a pad exposed on the first connection region, and a dummy electrode structure disposed adjacent to the electrode structure and including a plurality of dummy electrodes vertically stacked on the substrate. Each dummy electrode has a dummy pad exposed on the second connection region. The electrode structure includes a first stair structure and a second stair structure which each includes the pads of the electrodes exposed on the first connection region. The first stair structure extends along a first direction, and the second stair structure extends along a second direction that crosses the first direction.

公开(公告)号：US20170084696A1

公开(公告)日：2017-03-23

申请号：US15259941

申请日：2016-09-08

申请人： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

发明人： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

IPC分类号： H01L29/10 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

摘要： A three-dimensional semiconductor memory device includes a stack on a substrate including electrodes vertically stacked on a substrate, lower insulating patterns disposed between the stack and the substrate, the lower insulating patterns being adjacent to both sidewalls of the stack and being spaced apart from each other, a plurality of vertical structures penetrating the stack and being connected to the substrate, and a data storing pattern between the stack and the vertical structures, the data storing pattern including a portion disposed between the lowermost one of the electrodes and the substrate.