公开(公告)号：US08754681B2

公开(公告)日：2014-06-17

申请号：US13163605

申请日：2011-06-17

申请人： Julianne J. Zhu ,  David T. Hass

发明人： Julianne J. Zhu ,  David T. Hass

IPC分类号： H03L7/06

CPC分类号： H03L7/00

摘要： An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

摘要翻译： 描述了一种用于实现时钟管理系统的改进方法。 提供多部分锁相环电路以处理电路的不同时钟需要，其中多部分锁相环电路内的每个锁相环可以将时钟输出馈送到一个或多个除法器电路。 分频器电路可以专用于特定部件。 例如，SoC PLL可以产生时钟输出到专用于为内容地址存储器（CAM）组件提供时钟的SoC分频器。 这种方法允许时钟管理系统有效地生成具有可变电平频率的时钟信号，即使对于具有许多不同功能部分和组件的复杂电路也是如此。

公开(公告)号：US08725919B1

公开(公告)日：2014-05-13

申请号：US13164319

申请日：2011-06-20

申请人： Julianne J. Zhu ,  David T. Hass

发明人： Julianne J. Zhu ,  David T. Hass

IPC分类号： G06F13/00

CPC分类号： G06F9/4411 ,  G06F13/102 ,  G06F2213/0026 ,  G06F2213/0058

摘要： Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

摘要翻译： 公开了一种用于配置用于多处理器系统的设备的方法，其中属于不同处理器的设备被视为连接到标准化公共总线。 无论设备直接连接到哪个特定处理器，该设备一般可以通过标准化的公共总线进行识别和访问。 PCIe是可以采用的合适的标准总线类型的示例，其中用于每个处理器节点的设备被表示为PCIe设备。 因此，每个设备将作为PCIe设备出现在系统软件中。 然后可以使用PCIe控制器通过参考适当的设备标识符来访问设备。 这允许在任何处理器节点上访问任何设备，而对于每个单独的处理器节点没有单独和个性化的配置或驱动程序。

公开(公告)号：US20120319750A1

公开(公告)日：2012-12-20

申请号：US13163605

申请日：2011-06-17

申请人： Julianne J. Zhu ,  David T. Hass

发明人： Julianne J. Zhu ,  David T. Hass

IPC分类号： H03L7/08

CPC分类号： H03L7/00

摘要： An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

摘要翻译： 描述了一种用于实现时钟管理系统的改进方法。 提供多部分锁相环电路以处理电路的不同时钟需要，其中多部分锁相环电路内的每个锁相环可以将时钟输出馈送到一个或多个除法器电路。 分频器电路可以专用于特定部件。 例如，SoC PLL可以产生时钟输出到专用于为内容地址存储器（CAM）组件提供时钟的SoC分频器。 这种方法允许时钟管理系统有效地生成具有可变电平频率的时钟信号，即使对于具有许多不同功能部分和组件的复杂电路也是如此。