利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.01 秒)

    Method and system for V-BLAST detection with near maximum likelihood performance and low complexity
    1.
    发明授权
    Method and system for V-BLAST detection with near maximum likelihood performance and low complexity 有权
    具有接近最大似然性能和低复杂度的V-BLAST检测方法和系统

    公开(公告)号：US07693238B1

    公开(公告)日：2010-04-06

    申请号：US11650666

    申请日：2007-01-08

    申请人： G. Kalyana Krishnan ,  V. Umapathi Reddy

    发明人： G. Kalyana Krishnan ,  V. Umapathi Reddy

    IPC分类号： H04L27/06

    CPC分类号： H04L25/03305 ,  H04B7/0413 ,  H04L1/0656 ,  H04L25/0328

    摘要： Various embodiments of the present invention relate to a method and system for Vertical Bell Layered Space-Time (V-BLAST) detection with near Maximum Likelihood (ML) performance and low complexity. The V-BLAST system is a Multiple-Input Multiple-Output (MIMO) system. A receiver is provided that detects the data transmitted from the multiple transmitting antennas. The detection performance of such a method and system is better than that of linear receivers while keeping the complexity of the receiver marginally higher than that of the linear receivers. The detection performance of such a method and system is very close to that of the ML receiver while its complexity is much less than that of the ML receiver.

    摘要翻译： 本发明的各种实施例涉及具有接近最大似然（ML）性能和低复杂度的垂直钟形分层时空（V-BLAST）检测的方法和系统。 V-BLAST系统是多输入多输出（MIMO）系统。 提供了一种检测从多个发射天线发射的数据的接收机。 这种方法和系统的检测性能优于线性接收机，同时保持接收机的复杂度略高于线性接收机。 这种方法和系统的检测性能与ML接收机的检测性能非常接近，而其复杂度远小于ML接收机的检测性能。

    Parallel encoding for non-binary linear block code
    2.
    发明授权
    Parallel encoding for non-binary linear block code 有权
    非二进制线性块代码的并行编码

    公开(公告)号：US08949703B2

    公开(公告)日：2015-02-03

    申请号：US13430222

    申请日：2012-03-26

    申请人： Kalyana Krishnan ,  Hai-Jo Tarn

    发明人： Kalyana Krishnan ,  Hai-Jo Tarn

    IPC分类号： H03M13/00 ,  H03M13/13 ,  H03M13/11 ,  H03M13/05 ,  H03M13/21 ,  H03M13/15

    CPC分类号： H03M13/13 ,  H03M13/05 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1171 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/21 ,  H03M13/6502 ,  H03M13/6561

    摘要： An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

    摘要翻译： 编码器模块包括顺序耦合的P / L奇偶校验移位寄存器，其中奇偶校验移位寄存器的第一奇偶移位寄存器的输入耦合到编码器模块的输入端，奇偶校验位的最后奇偶移位寄存器的输出 移位寄存器耦合到编码器模块的输出，每个奇偶移位寄存器被配置为存储L个奇偶校验位。 编码器模块还包括一个包括P / L奇偶校验生成模块的反馈电路，其中奇偶校验生成模块中的每一个通过开关耦合到奇偶移位寄存器中对应的一个的输出，并且还耦合到第一奇偶校验的输入 移位寄存器，其中每个奇偶校验生成模块被配置为当其对应的开关闭合时，产生用于传输到第一奇偶移位寄存器的输入的L个奇偶校验位。

    PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE
    3.
    发明申请
    PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE 有权
    并行编码非二进制线性块代码

    公开(公告)号：US20130254639A1

    公开(公告)日：2013-09-26

    申请号：US13430222

    申请日：2012-03-26

    申请人： Kalyana Krishnan ,  Hai-Jo Tarn

    发明人： Kalyana Krishnan ,  Hai-Jo Tarn

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： H03M13/13 ,  H03M13/05 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1171 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/21 ,  H03M13/6502 ,  H03M13/6561

    摘要： An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

    摘要翻译： 编码器模块包括顺序耦合的P / L奇偶校验移位寄存器，其中奇偶校验移位寄存器的第一奇偶移位寄存器的输入耦合到编码器模块的输入端，奇偶校验位的最后奇偶移位寄存器的输出 移位寄存器耦合到编码器模块的输出，每个奇偶移位寄存器被配置为存储L个奇偶校验位。 编码器模块还包括一个包括P / L奇偶校验生成模块的反馈电路，其中奇偶校验生成模块中的每一个通过开关耦合到奇偶移位寄存器中对应的一个的输出，并且还耦合到第一奇偶校验的输入 移位寄存器，其中每个奇偶校验生成模块被配置为当其对应的开关闭合时，产生用于传输到第一奇偶移位寄存器的输入的L个奇偶校验位。