公开(公告)号：US20100312952A1

公开(公告)日：2010-12-09

申请号：US12790712

申请日：2010-05-28

申请人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Hervé Letourneur ,  Donald W. Smith ,  Manoj Gujral

发明人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Hervé Letourneur ,  Donald W. Smith ,  Manoj Gujral

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F13/1694 ,  G06F12/0638

摘要： A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

摘要翻译： 所公开的电路包括用于耦合到易失性存储器的电路，用于耦合到非易失性NAND闪速存储器的电路，以及电路：（i）从处理器接收易失性存储器请求，并通过访问易失性存储器来满足易失性存储器请求，以及 （ii）从处理器接收非易失性NOR闪存读取请求，并通过访问NAND闪速存储器和易失性存储器来满足NOR读取请求。 该电路还可以包括从另一个处理器接收易失性存储器请求并通过访问易失性存储器来满足来自另一个处理器的易失性存储器请求的电路，以及从其他处理器接收NAND闪存读取请求并满足NAND读取的电路 访问NAND闪存的请求。 描述包括该电路的多处理器系统，以及用于满足NOR闪存读取请求的方法。

公开(公告)号：US07730268B2

公开(公告)日：2010-06-01

申请号：US11465698

申请日：2006-08-18

申请人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Hervé Letourneur ,  Donald W. Smith ,  Manoj Gujral

发明人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Hervé Letourneur ,  Donald W. Smith ,  Manoj Gujral

IPC分类号： G06F13/00

CPC分类号： G06F13/1694 ,  G06F12/0638

摘要： A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

摘要翻译： 所公开的电路包括用于耦合到易失性存储器的电路，用于耦合到非易失性NAND闪速存储器的电路，以及电路：（i）从处理器接收易失性存储器请求，并通过访问易失性存储器来满足易失性存储器请求，以及 （ii）从处理器接收非易失性NOR闪存读取请求，并通过访问NAND闪速存储器和易失性存储器来满足NOR读取请求。 该电路还可以包括从另一个处理器接收易失性存储器请求并通过访问易失性存储器来满足来自另一个处理器的易失性存储器请求的电路，以及从其他处理器接收NAND闪存读取请求并满足NAND读取的电路 访问NAND闪存的请求。 描述包括该电路的多处理器系统，以及用于满足NOR闪存读取请求的方法。

公开(公告)号：US5896052A

公开(公告)日：1999-04-20

申请号：US912302

申请日：1997-05-27

申请人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

发明人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C8/06 ,  H03K3/037 ,  H03K5/00 ,  H03K5/13

CPC分类号： H03K3/0375 ,  G06F1/04 ,  G11C7/22 ,  G11C8/06

摘要： A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

摘要翻译： 一个多时钟脉冲同步器电路，具有IN部分，接收和存储规定的脉冲和输入时钟信号，并且响应地输出中间脉冲; 以及用于接收和存储中间脉冲的OUT部分，与某些输出时钟信号同步并对其进行处理以产生某些输出信号，以更好地避免亚稳态。

公开(公告)号：US5761446A

公开(公告)日：1998-06-02

申请号：US518353

申请日：1995-06-14

申请人： Greggory D. Donley ,  Manoj Gujral

发明人： Greggory D. Donley ,  Manoj Gujral

IPC分类号： G06F13/362 ,  G06F13/14

CPC分类号： G06F13/3625

摘要： In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.

摘要翻译： 在多处理器计算机系统中，许多“代理”可以竞争访问“资源”，一种改善“活锁”并防止任何此类代理人不适应于此类访问的方法，该方法包括：将系统安排到 包括连接多个处理器的仲裁单元和连接多个处理器的公共系统总线，以及包括在每个处理器中的回避单元，并且包括随机数生成器和自动“随机回退”，其导致无法保护访问的代理等待一个或 在重新尝试此类访问之前更多地给出随机时间段TB，其中每个所述时间段TB由随机数发生器提供，以便可能与竞争代理区分开。

公开(公告)号：US5822611A

公开(公告)日：1998-10-13

申请号：US464019

申请日：1995-06-05

申请人： Greggory D. Donley ,  Manoj Gujral ,  Paul N. Israel

发明人： Greggory D. Donley ,  Manoj Gujral ,  Paul N. Israel

IPC分类号： G06F12/08 ,  G06F13/38 ,  G06F13/14

CPC分类号： G06F12/0831

摘要： A method of arranging and operating a cache in a multi-processor computer system with N local processors, where a requesting device can request a cycle to be issued, where the method involves "posting" the "cycles", while also storing information for completing a cycle in a Queue and causing the requesting device to be issued "termination" immediately, rather than waiting for the cycle to reach its destination.

摘要翻译： 一种在具有N个本地处理器的多处理器计算机系统中布置和操作高速缓存的方法，其中请求设备可以请求发布周期，其中该方法涉及“发布”“周期”，同时还存储用于完成的信息 队列中的循环，并使得请求设备立即被发出“终止”，而不是等待循环到达其目的地。

公开(公告)号：US06223260B1

公开(公告)日：2001-04-24

申请号：US08926832

申请日：1997-09-10

申请人： Manoj Gujral ,  Brian Joseph Sassone ,  Laurence Paul Flora ,  David Edgar Castle

发明人： Manoj Gujral ,  Brian Joseph Sassone ,  Laurence Paul Flora ,  David Edgar Castle

IPC分类号： G06F1200

CPC分类号： G06F12/0811 ,  G06F12/0831

摘要： A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

摘要翻译： 数据处理系统包括：具有与其耦合的主存储器的系统总线; 多个高级缓存存储器，每个高速缓存存储器具有耦合到所述系统总线的第一端口和耦合到相应处理器总线的第二端口; 并且每个处理器总线通过相应的低级高速缓存存储器耦合到相应的数字计算机。 在高级缓存存储器中，数据字与相应的标记位一起存储，每个标记位将每个数据字标识为仅被共享，修改，无效或排他的四种状态之一存储。 在低级高速缓冲存储器中，数据字与相应的标记位一起存储，每个标记位将每个数据字识别为仅被共享，修改或无效的三种状态中的一种存储。

公开(公告)号：US6032231A

公开(公告)日：2000-02-29

申请号：US40193

申请日：1998-03-09

申请人： Manoj Gujral

发明人： Manoj Gujral

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0833

摘要： A method and system for arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase. The bus modules are arranged for access by a prescribed resource stage to facilitate "RETRY" operations. The method includes providing a Cache Tag and Address Compare, arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; and comparing subsequent address bus cycles to the contents of the Cache Tag so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access. The system provides components supporting the above method steps.

摘要翻译： 一种用于布置和操作具有“分割事务总线”架构的多处理器计算机服务器系统的方法和系统，包括以地址相位和周期阶段运行的总线模块。 总线模块被布置为通过规定的资源阶段进行访问以便于“重试”操作。 该方法包括提供缓存标签和地址比较，排列系统使得第一总线模块将资源级的地址存储在周期标签中; 并且将后续地址总线周期与缓存标签的内容进行比较，使得在给定“匹配”的情况下，“重试”方向被响应地发送到请求访问的任何其他总线模块。 该系统提供支持上述方法步骤的组件。

公开(公告)号：US5758104A

公开(公告)日：1998-05-26

申请号：US518352

申请日：1995-06-14

申请人： Manoj Gujral ,  Greggory D. Donley

发明人： Manoj Gujral ,  Greggory D. Donley

IPC分类号： G06F13/362 ,  G06F13/14

CPC分类号： G06F13/3625

摘要： In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sub.B before reattempting such access, with each said time period T.sub.B being provided by the random number generator so as to likely differentiate from competing agents.

摘要翻译： 在多处理器计算机系统中，许多“代理”可以竞争访问“资源”，一种改善“活锁”并防止任何此类代理人不适应于此类访问的方法，该方法包括：将系统安排到 包括连接多个处理器的仲裁单元和连接多个处理器的公共系统总线，以及包括在每个处理器中的回避单元，并且包括随机数生成器和自动“随机回退”，其导致无法保护访问的代理等待一个或 在重新尝试此类访问之前更多地给出随机时间段TB，其中每个所述时间段TB由随机数发生器提供，以便可能与竞争代理区分开。

公开(公告)号：US08060708B2

公开(公告)日：2011-11-15

申请号：US12790712

申请日：2010-05-28

申请人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

发明人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

IPC分类号： G06F12/00

CPC分类号： G06F13/1694 ,  G06F12/0638

摘要： A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

摘要翻译： 所公开的电路包括用于耦合到易失性存储器的电路，用于耦合到非易失性NAND闪速存储器的电路，以及电路：（i）从处理器接收易失性存储器请求，并通过访问易失性存储器来满足易失性存储器请求，以及 （ii）从处理器接收非易失性NOR闪存读取请求，并通过访问NAND闪速存储器和易失性存储器来满足NOR读取请求。 该电路还可以包括从另一个处理器接收易失性存储器请求并通过访问易失性存储器来满足来自另一个处理器的易失性存储器请求的电路，以及从其他处理器接收NAND闪存读取请求并满足NAND读取的电路 访问NAND闪存的请求。 描述包括该电路的多处理器系统，以及用于满足NOR闪存读取请求的方法。

公开(公告)号：US20080046638A1

公开(公告)日：2008-02-21

申请号：US11465698

申请日：2006-08-18

申请人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

发明人： Dinesh Maheshwari ,  Dinesh Ramanathan ,  Alakesh Chetia ,  Herve Letourneur ,  Donald W. Smith ,  Manoj Gujral

IPC分类号： G06F12/00

CPC分类号： G06F13/1694 ,  G06F12/0638

摘要： A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

摘要翻译： 所公开的电路包括用于耦合到易失性存储器的电路，用于耦合到非易失性NAND闪速存储器的电路，以及电路：（i）从处理器接收易失性存储器请求，并通过访问易失性存储器来满足易失性存储器请求，以及 （ii）从处理器接收非易失性NOR闪存读取请求，并通过访问NAND闪速存储器和易失性存储器来满足NOR读取请求。 该电路还可以包括从另一个处理器接收易失性存储器请求并通过访问易失性存储器来满足来自另一个处理器的易失性存储器请求的电路，以及从另一处理器接收NAND闪存读取请求并满足NAND读取 访问NAND闪存的请求。 描述包括该电路的多处理器系统，以及用于满足NOR闪存读取请求的方法。