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    Methods to avoid instability
    1.
    发明授权
    Methods to avoid instability 失效
    避免不稳定的方法

    公开(公告)号：US5896052A

    公开(公告)日：1999-04-20

    申请号：US912302

    申请日：1997-05-27

    申请人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

    发明人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

    IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C8/06 ,  H03K3/037 ,  H03K5/00 ,  H03K5/13

    CPC分类号： H03K3/0375 ,  G06F1/04 ,  G11C7/22 ,  G11C8/06

    摘要： A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

    摘要翻译： 一个多时钟脉冲同步器电路，具有IN部分，接收和存储规定的脉冲和输入时钟信号，并且响应地输出中间脉冲; 以及用于接收和存储中间脉冲的OUT部分，与某些输出时钟信号同步并对其进行处理以产生某些输出信号，以更好地避免亚稳态。

    Livelock avoidance
    2.
    发明授权
    Livelock avoidance 失效
    避免死锁

    公开(公告)号：US5761446A

    公开(公告)日：1998-06-02

    申请号：US518353

    申请日：1995-06-14

    申请人： Greggory D. Donley ,  Manoj Gujral

    发明人： Greggory D. Donley ,  Manoj Gujral

    IPC分类号： G06F13/362 ,  G06F13/14

    CPC分类号： G06F13/3625

    摘要： In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.

    摘要翻译： 在多处理器计算机系统中，许多“代理”可以竞争访问“资源”，一种改善“活锁”并防止任何此类代理人不适应于此类访问的方法，该方法包括：将系统安排到 包括连接多个处理器的仲裁单元和连接多个处理器的公共系统总线，以及包括在每个处理器中的回避单元，并且包括随机数生成器和自动“随机回退”，其导致无法保护访问的代理等待一个或 在重新尝试此类访问之前更多地给出随机时间段TB，其中每个所述时间段TB由随机数发生器提供，以便可能与竞争代理区分开。

    Avoiding instability
    3.
    发明授权
    Avoiding instability 失效
    避免不稳定

    公开(公告)号：US5638015A

    公开(公告)日：1997-06-10

    申请号：US493383

    申请日：1995-06-21

    申请人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

    发明人： Manoj Gujral ,  Greggory D. Donley ,  Paul N. Israel

    IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C8/06 ,  H03K3/037 ,  H03K5/00 ,  H03K5/13

    CPC分类号： H03K3/0375 ,  G06F1/04 ,  G11C7/22 ,  G11C8/06

    摘要： Described are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid "metastability", in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed impulses and input cock signals, and for responsively outputting intermediate signals: and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals which avoid metastability.

    摘要翻译： 描述了用于稳定从多个异步基站接收信号的存储设备的技术，特别是为了避免“亚稳态”，特别是具有用于接收和存储规定的脉冲和输入旋转信号的IN部分的多基准脉冲同步器电路，并且用于响应地 输出中间信号和OUT部分，用于接收和存储与某些输出时钟信号同步的中间脉冲，并处理它们以产生避免亚稳态的某些输出信号。

    Random delay subsystems
    5.
    发明授权
    Random delay subsystems 失效
    随机延迟子系统

    公开(公告)号：US5758104A

    公开(公告)日：1998-05-26

    申请号：US518352

    申请日：1995-06-14

    申请人： Manoj Gujral ,  Greggory D. Donley

    发明人： Manoj Gujral ,  Greggory D. Donley

    IPC分类号： G06F13/362 ,  G06F13/14

    CPC分类号： G06F13/3625

    摘要： In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sub.B before reattempting such access, with each said time period T.sub.B being provided by the random number generator so as to likely differentiate from competing agents.

    摘要翻译： 在多处理器计算机系统中，许多“代理”可以竞争访问“资源”，一种改善“活锁”并防止任何此类代理人不适应于此类访问的方法，该方法包括：将系统安排到 包括连接多个处理器的仲裁单元和连接多个处理器的公共系统总线，以及包括在每个处理器中的回避单元，并且包括随机数生成器和自动“随机回退”，其导致无法保护访问的代理等待一个或 在重新尝试此类访问之前更多地给出随机时间段TB，其中每个所述时间段TB由随机数发生器提供，以便可能与竞争代理区分开。

    Command packet packing to mitigate CRC overhead
    7.
    发明授权
    Command packet packing to mitigate CRC overhead 有权
    命令包打包以减轻CRC开销

    公开(公告)号：US07881303B2

    公开(公告)日：2011-02-01

    申请号：US11610191

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： H04L12/56 ,  G06F11/00

    CPC分类号： H04L1/0011 ,  H04L1/0007 ,  H04L1/0061 ,  H04L1/18

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。

    Command Packet Packing to Mitigate CRC Overhead
    8.
    发明申请
    Command Packet Packing to Mitigate CRC Overhead 有权
    指令包打包以减轻CRC开销

    公开(公告)号：US20080148131A1

    公开(公告)日：2008-06-19

    申请号：US11610191

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： G06F11/07 ,  H03M13/00

    CPC分类号： H04L1/0011 ,  H04L1/0007 ,  H04L1/0061 ,  H04L1/18

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。

    Cache word of interest latency organization
    9.
    发明授权
    Cache word of interest latency organization 有权
    缓存关键字延迟组织

    公开(公告)号：US07293141B1

    公开(公告)日：2007-11-06

    申请号：US11048350

    申请日：2005-02-01

    申请人： Greggory D. Donley

    发明人： Greggory D. Donley

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F12/0895 ,  G06F2212/271

    摘要： Techniques for improving cache latency include distributing cache lines across regions of the cache having various latencies. The latencies of the regions may vary as a function of the distance between an individual region of the cache and a cache controller. The cache controller may predict an addressable unit of interest for a next access to a data line stored in a cache line. The predicted addressable unit of interest is stored in a region of the cache having the lowest latency as compared to other regions of the cache. The addressable unit of interest may be a most-recently used addressable unit, an addressable unit sequentially following a most-recently used addressable unit, or determined by other criterion. The invention contemplates using at least one control bit to indicate which addressable unit is stored in the region having the lowest latency.

    摘要翻译： 用于改进高速缓存延迟的技术包括在具有不同延迟的缓存的区域上分配高速缓存行。 区域的延迟可以随高速缓存的单个区域和高速缓存控制器之间的距离的函数而变化。 高速缓存控制器可以预测用于对存储在高速缓存行中的数据线的下一次访问的可寻址单元。 与高速缓存的其他区域相比，预期的可寻址单元被存储在具有最低延迟的高速缓存的区域中。 感兴趣的可寻址单元可以是最近使用的可寻址单元，顺序地跟随最近使用的可寻址单元或由其他标准确定的可寻址单元。 本发明设想使用至少一个控制位来指示在具有最低延迟的区域中存储哪个可寻址单元。