公开(公告)号：US07687337B2

公开(公告)日：2010-03-30

申请号：US11779318

申请日：2007-07-18

申请人： Da Zhang ,  Mark C. Foisy

发明人： Da Zhang ,  Mark C. Foisy

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

摘要翻译： 通过提供半导体层并形成覆盖半导体层的控制电极来形成晶体管。 半导体层的一部分被去除控制电极的横向，以在控制电极的相对侧上形成第一凹部和第二凹部。 第一应力器形成在第一凹槽内并具有第一掺杂分布。 第二应力器形成在第二凹槽内并具有第一掺杂分布。 形成第三应激源，覆盖第一应激源。 第三应力源具有比第一轮廓具有更高的电极电流掺杂浓度的第二掺杂分布。 覆盖第二应激源的第四应力器形成并具有第二掺杂分布。 晶体管的第一电流电极和第二电流电极分别包括第三应力源和第四应力源的至少一部分。

公开(公告)号：US20090020783A1

公开(公告)日：2009-01-22

申请号：US11779318

申请日：2007-07-18

申请人： Da Zhang ,  Mark C. Foisy

发明人： Da Zhang ,  Mark C. Foisy

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

摘要翻译： 通过提供半导体层并形成覆盖半导体层的控制电极来形成晶体管。 半导体层的一部分被去除控制电极的横向，以在控制电极的相对侧上形成第一凹部和第二凹部。 第一应力器形成在第一凹槽内并具有第一掺杂分布。 第二应力器形成在第二凹槽内并具有第一掺杂分布。 形成第三应激源，覆盖第一应激源。 第三应力源具有比第一轮廓具有更高的电极电流掺杂浓度的第二掺杂分布。 覆盖第二应激源的第四应力器形成并具有第二掺杂分布。 晶体管的第一电流电极和第二电流电极分别包括第三应力源和第四应力源的至少一部分。

公开(公告)号：US07442621B2

公开(公告)日：2008-10-28

申请号：US10996319

申请日：2004-11-22

申请人： Marius K. Orlowski ,  Mark C. Foisy ,  Olubunmi O. Adetutu

发明人： Marius K. Orlowski ,  Mark C. Foisy ,  Olubunmi O. Adetutu

IPC分类号： H01L21/76

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878

摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

摘要翻译： 半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。 在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。 衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。 可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。 可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。 因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

公开(公告)号：US07344933B2

公开(公告)日：2008-03-18

申请号：US11324510

申请日：2006-01-03

申请人： Sinan Goktepeli ,  Mark C. Foisy

发明人： Sinan Goktepeli ,  Mark C. Foisy

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  Y10S438/933

摘要： A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.

摘要翻译： 公开了形成具有覆盖在化合物半导体层上的栅极结构的晶体管的延伸区域的方法。 在深源极/漏极注入之前或之后使用退火将掺杂剂从与栅极结构相邻的凸起区域扩散到栅极结构下方的位置。 当来自凸起区域的掺杂剂在深源/漏植入之前扩散时，可以使用非扩散激活过程来激活源极/漏极注入。