公开(公告)号：US07687337B2

公开(公告)日：2010-03-30

申请号：US11779318

申请日：2007-07-18

申请人： Da Zhang ,  Mark C. Foisy

发明人： Da Zhang ,  Mark C. Foisy

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

摘要翻译： 通过提供半导体层并形成覆盖半导体层的控制电极来形成晶体管。 半导体层的一部分被去除控制电极的横向，以在控制电极的相对侧上形成第一凹部和第二凹部。 第一应力器形成在第一凹槽内并具有第一掺杂分布。 第二应力器形成在第二凹槽内并具有第一掺杂分布。 形成第三应激源，覆盖第一应激源。 第三应力源具有比第一轮廓具有更高的电极电流掺杂浓度的第二掺杂分布。 覆盖第二应激源的第四应力器形成并具有第二掺杂分布。 晶体管的第一电流电极和第二电流电极分别包括第三应力源和第四应力源的至少一部分。

公开(公告)号：US20090020783A1

公开(公告)日：2009-01-22

申请号：US11779318

申请日：2007-07-18

申请人： Da Zhang ,  Mark C. Foisy

发明人： Da Zhang ,  Mark C. Foisy

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

摘要翻译： 通过提供半导体层并形成覆盖半导体层的控制电极来形成晶体管。 半导体层的一部分被去除控制电极的横向，以在控制电极的相对侧上形成第一凹部和第二凹部。 第一应力器形成在第一凹槽内并具有第一掺杂分布。 第二应力器形成在第二凹槽内并具有第一掺杂分布。 形成第三应激源，覆盖第一应激源。 第三应力源具有比第一轮廓具有更高的电极电流掺杂浓度的第二掺杂分布。 覆盖第二应激源的第四应力器形成并具有第二掺杂分布。 晶体管的第一电流电极和第二电流电极分别包括第三应力源和第四应力源的至少一部分。

公开(公告)号：US08643217B2

公开(公告)日：2014-02-04

申请号：US12674936

申请日：2007-12-26

申请人： Thomas Gietzold ,  Jeffrey J. Burchill ,  Da Zhang ,  Weiqian Hu

发明人： Thomas Gietzold ,  Jeffrey J. Burchill ,  Da Zhang ,  Weiqian Hu

IPC分类号： H02J3/00

CPC分类号： H02P9/02 ,  Y10T307/675

摘要： An apparatus and method for boosting output of a generator set are provided. The output of the generator set is connected to an electrical load. The apparatus includes an energy storage unit, and a power-electronic unit. The energy storage unit uses batteries and capacitors to store electric energy. The power-electronic unit measures an electrical parameter of the output of the generator set. Based on the measured electrical parameter and a predefined criterion, the power-electronic unit determines additional energy required by the electrical load. Thereafter, the power-electronic unit supplies the additional energy to the electrical load. The additional energy is drawn from the energy storage unit.

摘要翻译： 提供了一种用于提升发电机组的输出的装置和方法。 发电机组的输出连接到电气负载。 该装置包括能量存储单元和电力电子单元。 储能单元使用电池和电容器来储存电能。 电力电子单元测量发电机组输出的电气参数。 基于测量的电参数和预定标准，功率电子单元确定电负载所需的附加能量。 此后，电力电子单元向电负载提供额外的能量。 额外的能量从能量存储单元中抽出。

公开(公告)号：US08106462B2

公开(公告)日：2012-01-31

申请号：US12687374

申请日：2010-01-14

申请人： Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

发明人： Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

摘要翻译： 集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。 该对互补晶体管包括第一晶体管和第二晶体管。 该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。 第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。 第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

公开(公告)号：US07795089B2

公开(公告)日：2010-09-14

申请号：US11680219

申请日：2007-02-28

申请人： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

发明人： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772

摘要： A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

摘要翻译： 在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。 第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。 在第一和第二区域上形成第一绝缘层。 第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。 从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。 半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。 在凹部中外延生长半导体材料。 去除第一绝缘层的剩余部分。

公开(公告)号：US20100078687A1

公开(公告)日：2010-04-01

申请号：US12242078

申请日：2008-09-30

申请人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

发明人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

IPC分类号： H01L21/8238 ,  H01L29/04

CPC分类号： H01L21/823807 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/7843

摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).

摘要翻译： 一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率 蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72） 结构（26,36）和拉伸侧壁间隔物（62）。 在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94） 栅极结构（26,36）和侧壁间隔物（92）。

公开(公告)号：US07538002B2

公开(公告)日：2009-05-26

申请号：US11361171

申请日：2006-02-24

申请人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

发明人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

公开(公告)号：US07494856B2

公开(公告)日：2009-02-24

申请号：US11393340

申请日：2006-03-30

申请人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78684

摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

摘要翻译： 半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 可以使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿式蚀刻来蚀刻源极/漏极区域。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

公开(公告)号：US20080296620A1

公开(公告)日：2008-12-04

申请号：US12174357

申请日：2008-07-16

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/66795 ,  H01L29/78684

摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

摘要翻译： 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

公开(公告)号：US20060228863A1

公开(公告)日：2006-10-12

申请号：US11092291

申请日：2005-03-29

申请人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

发明人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

摘要翻译： 通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。 在控制电极的侧壁附近形成绝缘层。 注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下 半导体器件。 第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。 在第一沟槽和第二沟槽内形成含有相对于半导体衬底的不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。