公开(公告)号：US20090298555A1

公开(公告)日：2009-12-03

申请号：US12537495

申请日：2009-08-07

申请人： Mark D. Matson ,  Bruce E. Edwards

发明人： Mark D. Matson ,  Bruce E. Edwards

IPC分类号： H04M1/00

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  H04B1/1615 ,  H04W52/0235 ,  Y02D70/122 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/40

摘要： A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的无线通信设备处理器的电源管理方案。 通过将处理器控制逻辑中的睡眠和唤醒模式转换控制结合在一起，提供了降低延迟的功率节省，从而避免了使用精心设计的信令机制对以硬件为中心的解决方案。 由MAC解决方案控制的完全集成的电源管理与分阶段的唤醒操作相比，在待机模式下的传统无线局域网解决方案的功耗要低。

公开(公告)号：US07043516B1

公开(公告)日：2006-05-09

申请号：US09042417

申请日：1998-03-13

申请人： Gilbert M. Wolrich ,  Mark D. Matson ,  John D. Clouser

发明人： Gilbert M. Wolrich ,  Mark D. Matson ,  John D. Clouser

IPC分类号： G06F7/00

CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/74

摘要： The shifters (30, 32) that a floating-point processor (10)'s addition pipeline (14) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction than for addition. As a result, the addition pipeline's rounding circuitry (160, 166) does not need to be capable of adding round bits in as many positions as it would without the shift difference, so it can be simpler and faster. Similarly, circuitry (164a–g and 188) employed for normalization after addition and subtraction can be simpler because it does not have to implement as shift options.

摘要翻译： 浮点处理器（10）的附加流水线（14）用于在加或减之前对浮点操作数的尾数进行对准或归一化的移位器（30,32）将给定的尾数对向左移位一个位， 减去比添加。 结果，加法管线的舍入电路（160,166）不需要能够在没有偏移差的情况下以尽可能多的位置添加圆形位，因此可以更简单和更快。 类似地，在加法和减法之后用于归一化的电路（164a-g和188）可以更简单，因为它不需要实现作为移位选项。

公开(公告)号：US08275423B2

公开(公告)日：2012-09-25

申请号：US12537495

申请日：2009-08-07

申请人： Mark D. Matson ,  Bruce E. Edwards

发明人： Mark D. Matson ,  Bruce E. Edwards

IPC分类号： H04M1/00 ,  H04B1/38 ,  H04B1/16 ,  H04B1/04 ,  H01Q11/12

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  H04B1/1615 ,  H04W52/0235 ,  Y02D70/122 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/40

摘要： A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的无线通信设备处理器的电源管理方案。 通过将处理器控制逻辑中的睡眠和唤醒模式转换控制结合在一起，提供了降低延迟的功率节省，从而避免了使用精心设计的信令机制对以硬件为中心的解决方案。 由MAC解决方案控制的完全集成的电源管理与分阶段的唤醒操作相比，在待机模式下的传统无线局域网解决方案的功耗要低。

公开(公告)号：US06366942B1

公开(公告)日：2002-04-02

申请号：US09281501

申请日：1999-03-30

申请人： Roy W. Badeau ,  William Robert Grundmann ,  Mark D. Matson ,  Sridhar Samudrala

发明人： Roy W. Badeau ,  William Robert Grundmann ,  Mark D. Matson ,  Sridhar Samudrala

IPC分类号： G06F750

CPC分类号： G06F7/49947 ,  G06F7/485

摘要： A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both a low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low rounding bit increment result. In this manner, the present rounding adder circuit eliminates the need to perform a no increment calculation used to select a result, as in the prior art. Through the use of full adders, the circuit not only accounts for the round increment bit, but can accept increment bits at any bit position to perform operations such as two's complement, thus further reducing the operations required to perform a desired floating point mathematical operation.

摘要翻译： 提供了一种用于对浮点数进行操作的方法和装置，其接受两个浮点数作为操作数，以便执行加法，提供了可以接受操作数的舍入加法器电路和各种位位置处的舍入增量位。 该电路在所需的位位置使用完全加法器，以适应每个操作数和舍入位的位。 由于在开始时将注入舍入位的适当位置可能是未知的，所以提供相应的低和高增量位加法电路来计算低和高增量舍入比特条件的结果。 最终结果是根据低舍入位增量结果的最高有效位来选择的。 以这种方式，现有的舍入加法器电路消除了如现有技术中那样执行用于选择结果的无增量计算的需要。 通过使用全加法器，该电路不仅考虑了循环增量位，而且可以在任何位位置接受增量位，以执行诸如二进制补码的操作，从而进一步减少执行所需浮点数学运算所需的操作。

公开(公告)号：US07200379B2

公开(公告)日：2007-04-03

申请号：US10810199

申请日：2004-03-26

申请人： Bruce E. Edwards ,  Mark D. Matson

发明人： Bruce E. Edwards ,  Mark D. Matson

IPC分类号： H04B1/16

CPC分类号： H04W52/029 ,  Y02D70/122 ,  Y02D70/142 ,  Y02D70/144

摘要： A power management scheme for a wireless communications device substantially implemented on a single CMOS integrated circuit is described. The present invention provides a method and apparatus for generating first and second clock signals for a wireless communication device, with the first and second clock signals corresponding first and second power levels, depending on the operating mode of the wireless communication unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having the high-speed, high-accuracy characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a frequency and quality sufficient to maintain efficient operation of the digital modules in the wireless communication device. In the second operational state, the high-speed, high-accuracy clock is replaced by a low-power oscillator when the wireless communication unit is operating in a low power mode.

公开(公告)号：US06779012B2

公开(公告)日：2004-08-17

申请号：US10419454

申请日：2003-04-18

申请人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： G06F7552

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

摘要翻译： 用于执行产生根或商的平方根或除法运算的计算机方法和装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。

公开(公告)号：US06360241B1

公开(公告)日：2002-03-19

申请号：US09294597

申请日：1999-04-20

申请人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： B06F700

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

摘要翻译： 本发明提供用于执行产生根或商的平方根或除法运算的计算机装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。

公开(公告)号：US6144228A

公开(公告)日：2000-11-07

申请号：US340774

申请日：1999-06-28

申请人： Mark D. Matson ,  Sridhar Samudrala ,  Robert J. Dupcak

发明人： Mark D. Matson ,  Sridhar Samudrala ,  Robert J. Dupcak

IPC分类号： G06F7/48 ,  G06F7/50 ,  G06F7/52 ,  G06F7/535 ,  H03K19/0948

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.

摘要翻译： 提出了一种方法和装置，用于有效地实现产生一组相互排斥的输出信号的逻辑和算术功能。 这种逻辑系列包括实现所需逻辑功能的NMOS晶体管网络。 耦合到该网络是用于提供逻辑电平恢复并用于补偿由于NMOS晶体管的任何电压降的最小数量的PMOS器件。 通过这样的结构，提高了逻辑功能的速度，面积和功耗特性。

公开(公告)号：US6084455A

公开(公告)日：2000-07-04

申请号：US133235

申请日：1998-08-13

申请人： Mark D. Matson

发明人： Mark D. Matson

IPC分类号： H03K3/013 ,  H03K3/356 ,  H03K3/037

CPC分类号： H03K3/013 ,  H03K3/356113

摘要： A high-speed CMOS latch includes at each storage node a pull-up P-transistor with its gate tied to a dynamic node, and a pull-down N-transistor with its gate controlled by the inverse of the states of the remaining dynamic nodes. The P-transistor drives the storage node high to VDD, and the N-transistor drives the node low to VSS, as appropriate. During evaluation, one dynamic node discharges to a low state and in response each storage node is driven relatively quickly to the desired high or low state through either the associated pull-up or pull-down transistor. Precharging P-transistors drive the dynamic nodes high during precharge periods. As the dynamic nodes go high, they turn off all of the pull-up and pull-down transistors that drive the latch storage nodes, and the latch retains the evaluated state of the dynamic nodes until the start of the next evaluation cycle. Accordingly, the latch does not require a separate clock.

摘要翻译： 高速CMOS锁存器包括在每个存储节点处具有其栅极连接到动态节点的上拉P晶体管，以及其栅极由其余动态节点的状态的反相控制的下拉N晶体管 。 P晶体管将存储节点驱动为高电平至VDD，并且N晶体管将节点驱动为低电平至VSS。 在评估期间，一个动态节点放电到低状态，并且响应每个存储节点通过相关联的上拉或下拉晶体管相对快速地驱动到期望的高或低状态。 在预充电期间，P型晶体管预充电驱动动态节点。 当动态节点变高时，它们关闭驱动锁存器存储节点的所有上拉和下拉晶体管，并且锁存器保留动态节点的评估状态，直到下一个评估周期开始。 因此，锁存器不需要单独的时钟。

公开(公告)号：US08467837B2

公开(公告)日：2013-06-18

申请号：US13617473

申请日：2012-09-14

申请人： Mark D. Matson ,  Bruce E. Edwards

发明人： Mark D. Matson ,  Bruce E. Edwards

IPC分类号： H04M1/00 ,  H04B1/38 ,  H04B1/16 ,  H04B1/04 ,  H01Q11/12

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  H04B1/1615 ,  H04W52/0235 ,  Y02D70/122 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/40

摘要： A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.