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    Semiconductor device
    1.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07573109B2

    公开(公告)日：2009-08-11

    申请号：US11528654

    申请日：2006-09-28

    申请人： Shinji Kunori ,  Hiroaki Shishido ,  Masato Mikawa ,  Kosuke Ohshima ,  Masahiro Kuriyama ,  Mizue Kitada

    发明人： Shinji Kunori ,  Hiroaki Shishido ,  Masato Mikawa ,  Kosuke Ohshima ,  Masahiro Kuriyama ,  Mizue Kitada

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/47 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90

    摘要翻译： 具有高抗破坏性能的半导体器件。 半导体器件1包括同心地设置在第一导电类型的电阻层15上的第二导电类型的保护掩埋区域44b，并且在保护掩埋区域44b的内侧设置有基极扩散区域17a，并且设置第二导电类型的基极掩埋区域44a 在基底扩散区域17a的底面上。 在相同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为Wm1，不同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为Wm2， 44b是WPE。 当Wm1

    Semiconductor device
    2.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20070069323A1

    公开(公告)日：2007-03-29

    申请号：US11528654

    申请日：2006-09-28

    申请人： Shinji Kunori ,  Hiroaki Shishido ,  Masato Mikawa ,  Kosuke Ohshima ,  Masahiro Kuriyama ,  Mizue Kitada

    发明人： Shinji Kunori ,  Hiroaki Shishido ,  Masato Mikawa ,  Kosuke Ohshima ,  Masahiro Kuriyama ,  Mizue Kitada

    IPC分类号： H01L23/58

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/47 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90

    摘要翻译： 具有高抗破坏性能的半导体器件。 半导体器件1包括同心地设置在第一导电类型的电阻层15上的第二导电类型的保护掩埋区域44b，并且在保护掩埋区域44b的内部设置基极扩散区域17a，并且在第二导电类型的第二导电类型的基极掩埋区域44a 导电类型设置在基底扩散区域17a的底表面上。 在相同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为W m 1，在不同的基底扩散区域17的底部的相邻的基底掩埋区域44a之间的距离 a是Wm 2 2，并且防护埋入区域44b之间的距离是W PE 2 。 第一导电类型的杂质量Q <1> 1和第二导电类型的杂质量Q 2> 2 的比率包括在最内侧保护埋入区44的宽度方向中心的内侧 当Wm <1时，b是0.90 。 当W 1 2 时，该比例为Q 2 / Q 1 /SUB><0.92当WM 2 PE 时，该比例为1.10 / Q <1> 。