公开(公告)号：US5784606A

公开(公告)日：1998-07-21

申请号：US768060

申请日：1996-12-16

申请人： Thomas Alan Hoy ,  Terence Matthew Potter ,  Paul Charles Rossbach

发明人： Thomas Alan Hoy ,  Terence Matthew Potter ,  Paul Charles Rossbach

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4812

摘要： A method and system in a data processing system are disclosed for efficiently handling exceptions. The data processing system includes a register for storing indications of multiple instructions while the multiple instructions are being concurrently processed. An exception is generated within the data processing system. A determination is made whether the exception was generated by one of the multiple instructions. In response to a determination that one of the multiple instructions generated the exception, a determination is then made whether an indication of the instruction which generated the exception is stored in a particular position within a register within the data processing system. In response to a determination that the indication of the instruction is stored in the particular position within the register, the exception is associated with a first priority group. In response to a determination that the indication of the instruction is not stored in the particular position within the register, the exception is associated with a second priority group. In response to a determination that the indication of the instruction did not generate the exception, the exception is associated with the second priority group.

摘要翻译： 公开了一种数据处理系统中的方法和系统，用于有效地处理异常。 数据处理系统包括一个寄存器，用于存储多个指令同时处理多个指令的指示。 在数据处理系统中产生异常。 确定异常是否由多个指令之一生成。 响应于多个指令中的一个指令产生异常的确定，然后确定产生异常的指令的指示是否存储在数据处理系统内的寄存器内的特定位置。 响应于指示的指示被存储在寄存器内的特定位置的确定，该异常与第一优先级组相关联。 响应于指示的指示未​​被存储在寄存器内的特定位置的确定，该异常与第二优先级组相关联。 响应于指示的指示没有产生异常的确定，该异常与第二优先级组相关联。

公开(公告)号：US5715427A

公开(公告)日：1998-02-03

申请号：US592143

申请日：1996-01-26

申请人： David Daniel Barrera ,  Bahador Rastegar, deceased ,  Paul Charles Rossbach

发明人： David Daniel Barrera ,  Bahador Rastegar, deceased ,  Paul Charles Rossbach

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/127 ,  G06F12/0864 ,  G06F12/123

摘要： A cache memory uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. In a semi-associative instruction cache, with the CAM and eight cache lines grouped together to form camlets, a binary index is used to address one camlet in the cache array, and the effective address tag match is used to select a potential line within the camlet in accessing data stored in the cache array. Since an E-tag match causes that cache line's wordline to activate, proper cache operation requires that no two (or more) E-tags within a camlet have the same match criteria (ECAM entry); the invalidation of entries is done to prevent this from happening. Due to the mapping of the effective address into the E-tag CAM and the camlet binary index, addresses that are 1-Meg apart point to the same camlet and have the same ECAM tag. The method thus employs a semi-associative cache having cache lines configured in camlets of, for example, eight lines per camlet. An LRU indication is stored in each camlet showing which line was least-recently-used. Upon occurrence of a cache replacement operation, it is determined whether or not a replacement line has a tag matching a line that is already in the camlet, and, if so, this line is invalidated and it is indicated to be the least-recently-used line. The next replacement goes to this line, whereas otherwise it would have appeared to be the most-recently-used since its wordline went high for the invalidate operation.

摘要翻译： 高速缓冲存储器使用内容寻址标签比较阵列（CAM）来确定是否发生匹配。 在半关联指令高速缓存中，将CAM和8个缓存行分组在一起形成camlet，使用二进制索引来对高速缓存阵列中的一个camlet进行寻址，并且使用有效地址标签匹配来选择 camlet访问存储在缓存数组中的数据。 由于电子标签匹配导致该高速缓存行的字线被激活，正确的高速缓存操作要求在小区内没有两个（或更多）电子标签具有相同的匹配标准（ECAM条目）; 完成条目的无效以防止这种情况发生。 由于将有效地址映射到E-tag CAM和camlet二进制索引中，1-Meg的地址指向同一个小区并具有相同的ECAM标签。 因此，该方法采用半联结高速缓存，其具有配置在例如每个小区8个线路的小区中的高速缓存线。 每个小白鼠存储LRU指示，显示哪条线最近被使用。 在发生高速缓存替换操作时，确定替换线是否具有与已经在该小区中的线路匹配的标签，并且如果是，则该线路被无效，并且被指示为最近最近 - 使用线。 接下来的替代方案是这样的，而否则它似乎是最近使用的，因为它的字线变得非常高，无效操作。

公开(公告)号：US5974535A

公开(公告)日：1999-10-26

申请号：US853009

申请日：1997-05-09

申请人： Chih-Jui Ray Peng ,  Daniel Chen Chow ,  Terence Matthew Potter ,  Paul Charles Rossbach

发明人： Chih-Jui Ray Peng ,  Daniel Chen Chow ,  Terence Matthew Potter ,  Paul Charles Rossbach

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30094 ,  G06F9/30101 ,  G06F9/384 ,  G06F9/3863 ,  G06F9/3885

摘要： A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.

摘要翻译： 公开了允许并行处理多个条件分支指令的数据处理系统中的方法和系统。 在处理系统内建立条件寄存器。 在处理系统的单个周期期间调度第一和第二条件分支指令。 在推测性地执行第一条件转移指令之前，存储条件寄存器的第一副本。 在推测执行第二条件分支指令之前，存储条件寄存器的第二副本。 同时维护条件寄存器的多个副本，使得可以在处理系统的单个周期期间同时处理第一和第二条件转移指令。

公开(公告)号：US5765017A

公开(公告)日：1998-06-09

申请号：US785149

申请日：1997-01-13

申请人： Thomas Alan Hoy ,  Terence M. Potter ,  Paul Charles Rossbach

发明人： Thomas Alan Hoy ,  Terence M. Potter ,  Paul Charles Rossbach

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/76

CPC分类号： G06F9/384

摘要： A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An array is established having multiple entry fields for storing multiple entries. Each of the multiple entry fields is associated with a different one of the plurality of registers. A status of each of the plurality of registers is determined. A plurality of partitions are established within the array. Each of the partitions are concurrently accessible by the data processing system. A plurality of the multiple entry fields are associated with one of the plurality partitions. An entry is stored in each of the multiple entry field. The entry includes the status of each of the plurality of registers. Each entry is associated with one of the partitions so that a plurality of the multiple entries may be concurrently accessed.

摘要翻译： 公开了一种数据处理系统中的方法和系统，用于有效地管理包括在数据处理系统中的多个寄存器中的每一个的状态的指示。 建立具有用于存储多个条目的多个输入字段的数组。 多个输入字段中的每一个与多个寄存器中的不同的寄存器相关联。 确定多个寄存器中的每一个的状态。 在阵列内建立多个分区。 每个分区可由数据处理系统同时访问。 多个输入字段中的多个与多个分区之一相关联。 一个条目存储在多个输入字段的每一个中。 该条目包括多个寄存器中的每一个的状态。 每个条目与一个分区相关联，使得多个多个条目可以被同时访问。

公开(公告)号：US5901307A

公开(公告)日：1999-05-04

申请号：US684720

申请日：1996-07-22

申请人： Terence Matthew Potter ,  Paul Charles Rossbach ,  Thomas Luther Thomas, Jr.

发明人： Terence Matthew Potter ,  Paul Charles Rossbach ,  Thomas Luther Thomas, Jr.

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3848

摘要： A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

摘要翻译： 公开了一种用于推测性地执行分支指令的处理器和方法。 该处理器包括：分支预测单元，用于预测推测分支指令的分辨率，该分支预测单元可选择性地配置，使得仅响应于推测分支指令的地址或响应于分支历史信号预测推测分支指令的分辨率 至少一个先前执行的分支指令。 处理器还包括用于响应于推测分支指令的预测分辨率来确定目标地址的地址计算单元。 在一个实施例中，处理器还包括用于动态配置分支预测逻辑的配置逻辑。

公开(公告)号：US5765221A

公开(公告)日：1998-06-09

申请号：US767568

申请日：1996-12-16

申请人： Paul Charles Rossbach ,  Chin-Cheng Kau ,  David Stephen Levitan

发明人： Paul Charles Rossbach ,  Chin-Cheng Kau ,  David Stephen Levitan

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F12/04

CPC分类号： G06F9/342 ,  G06F9/30094 ,  G06F9/32 ,  G06F9/321 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802

摘要： An improved method of addressing within a pipelined processor having an address bit width of m+n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.

摘要翻译： 公开了一种具有地址位宽度为m + n位的流水线处理器内的寻址改进方法，其包括存储对应于第一地址范围的m个高位，其包含在流水线处理器内执行的选定的多个数据。 还存储与所选择的多个数据中的每一个相关联的n个低位地址。 在确定要在处理器中执行的后续数据的地址之后，获取随后的数据。 响应于获取具有在第一地址范围之外的地址的后续数据，状态寄存器被设置为两种状态中的第一状态，以指示需要对第一地址寄存器的更新。 响应于将状态寄存器设置为两个状态中的第二个状态，随后的数据被调度以在流水线处理器内执行。 然后存储随后数据的n个低位，从而减少了在流水线处理器内执行的指令的存储地址所需的存储器。