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1.发明申请公开(公告)号：US20100057404A1
公开(公告)日：2010-03-04
申请号：US12201877
申请日：2008-08-29
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Techniques for processor chip power management and performance optimization are provided. In one aspect, a method for maximizing performance of a processor chip within a given power consumption budget is provided. The method comprises the following steps. A power consumption and performance of the processor chip at all possible voltage level and frequency combinations is predicted. The processor chip is adjusted to the voltage level and frequency combination that provides the highest performance while having a power consumption that does not exceed the power budget. After a time interval t1, the frequency of the processor chip is varied to accommodate for any shift in workload to maintain the highest performance within the power budget. After a time interval t2, the adjust and vary steps are repeated, wherein time interval t2 is greater than time interval t1.
摘要翻译： 提供了处理器芯片功率管理和性能优化的技术。 在一个方面，提供了一种用于在给定功耗预算内最大化处理器芯片的性能的方法。 该方法包括以下步骤。 预测在所有可能的电压电平和频率组合下的处理器芯片的功耗和性能。 处理器芯片被调整到提供最高性能的电压电平和频率组合，同时具有不超过功率预算的功耗。 在时间间隔t1之后，改变处理器芯片的频率以适应任何工作量的变化，以在功率预算内维持最高性能。 在时间间隔t2之后，重复调整和改变步骤，其中时间间隔t2大于时间间隔t1。
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2.发明授权公开(公告)号：US06993740B1
公开(公告)日：2006-01-31
申请号：US09542024
申请日：2000-04-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods contemplated herein significantly reduce the time, complexity and potential for errors associated with systems-on-chip (SoC) integration.
摘要翻译： 一种用于在具有数百个引脚的复杂知识产权（IP）内核之间创建正确构建互连的方法和算法。 本文中考虑的方法显着地减少了与片上系统（SoC）集成相关的错误的时间，复杂性和潜力。
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公开(公告)号：US06324680B1
公开(公告)日：2001-11-27
申请号：US09385307
申请日：1999-08-30
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method for synthesizing aggregate data types, in accordance with the present invention, includes representing aggregate data types in a control data flow graph, by representing aggregate objects as operand nodes, and operations on the aggregate objects as operation nodes. One-dimensional bit vectors are formed for the operand nodes, by recursively traversing through fields of the aggregate data type associated with the aggregate objects. Read and write operation nodes are formed in the control data flow graph for representing language constructs for accessing the aggregate objects. The control data flow graph is mapped onto hardware.
摘要翻译： 根据本发明的用于合成聚合数据类型的方法包括：通过将聚合对象表示为操作数节点，以及将作为操作节点的聚合对象的操作来表示控制数据流图中的聚合数据类型。 通过递归地遍历与聚合对象相关联的聚合数据类型的字段，为操作数节点形成一维位向量。 读写操作节点形成在控制数据流图中，用于表示用于访问聚合对象的语言结构。 控制数据流图被映射到硬件上。
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公开(公告)号：US20090070719A1
公开(公告)日：2009-03-12
申请号：US11853235
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
摘要翻译： 用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。 存储器可以提供逻辑块的延迟对锥形值。 该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。 系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。 锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。
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公开(公告)号：US07676779B2
公开(公告)日：2010-03-09
申请号：US11853235
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
CPC分类号： G06F17/5031
摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
摘要翻译： 用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。 存储器可以提供逻辑块的延迟对锥形值。 该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。 系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。 锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。
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公开(公告)号：US08001405B2
公开(公告)日：2011-08-16
申请号：US12201821
申请日：2008-08-29
CPC分类号： G06F1/3203
摘要： Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.
摘要翻译： 电源管理技术包括用于处理器芯片的电源管理的方法，其包括以下步骤。 为处理器芯片设置初始操作级别。 在预定的时间间隔之后，计算松弛。 如果松弛度大于零，则初始操作级别增加到下一级，否则保持初始操作级别。 在预定的时间间隔之后，重新计算松弛，并进一步包括累积的松弛。 如果重新计算的松弛大于零，则如果处理器芯片在初始操作电平下操作，则操作电平增加到下一个较高电平，否则如果处理器芯片为 在下一个更高的运行水平运行。 重新计算松弛的步骤，并将操作级别提高到下一级，或将操作级别恢复到初始操作级别。
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公开(公告)号：US20100058084A1
公开(公告)日：2010-03-04
申请号：US12201821
申请日：2008-08-29
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.
摘要翻译： 电源管理技术包括用于处理器芯片的电源管理的方法，其包括以下步骤。 为处理器芯片设置初始操作级别。 在预定的时间间隔之后，计算松弛。 如果松弛度大于零，则初始操作级别增加到下一级，否则保持初始操作级别。 在预定的时间间隔之后，重新计算松弛，并进一步包括累积的松弛。 如果重新计算的松弛大于零，则如果处理器芯片在初始操作电平下操作，则操作电平增加到下一个较高电平，否则如果处理器芯片为 在下一个更高的运行水平运行。 重新计算松弛的步骤，并将操作级别提高到下一级，或将操作级别恢复到初始操作级别。
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8.发明申请System to Identify Timing Differences from Logic Block Changes and Associated Methods 审中-公开识别与逻辑块更改和相关方法的时间差异的系统公开(公告)号：US20090070720A1
公开(公告)日：2009-03-12
申请号：US11853276
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Lawrence Lange , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri , Gebhard Weber
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Lawrence Lange , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri , Gebhard Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.
摘要翻译： 用于识别由于逻辑块变化引起的时序差异的系统，系统可以包括控制器和与控制器通信的存储器。 控制器可以提供先前逻辑块和当前逻辑块的延迟值。 该系统还可以包括一个定时建模器，用于将先前逻辑块的延迟值与用于定时分析的当前逻辑块进行比较。 系统还可以包括基于先前逻辑块和当前逻辑块比较来提供报告的接口。
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