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1.发明申请公开(公告)号：US20100057404A1
公开(公告)日：2010-03-04
申请号：US12201877
申请日：2008-08-29
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Techniques for processor chip power management and performance optimization are provided. In one aspect, a method for maximizing performance of a processor chip within a given power consumption budget is provided. The method comprises the following steps. A power consumption and performance of the processor chip at all possible voltage level and frequency combinations is predicted. The processor chip is adjusted to the voltage level and frequency combination that provides the highest performance while having a power consumption that does not exceed the power budget. After a time interval t1, the frequency of the processor chip is varied to accommodate for any shift in workload to maintain the highest performance within the power budget. After a time interval t2, the adjust and vary steps are repeated, wherein time interval t2 is greater than time interval t1.
摘要翻译： 提供了处理器芯片功率管理和性能优化的技术。 在一个方面，提供了一种用于在给定功耗预算内最大化处理器芯片的性能的方法。 该方法包括以下步骤。 预测在所有可能的电压电平和频率组合下的处理器芯片的功耗和性能。 处理器芯片被调整到提供最高性能的电压电平和频率组合，同时具有不超过功率预算的功耗。 在时间间隔t1之后，改变处理器芯片的频率以适应任何工作量的变化，以在功率预算内维持最高性能。 在时间间隔t2之后，重复调整和改变步骤，其中时间间隔t2大于时间间隔t1。
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公开(公告)号：US08001405B2
公开(公告)日：2011-08-16
申请号：US12201821
申请日：2008-08-29
CPC分类号： G06F1/3203
摘要： Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.
摘要翻译： 电源管理技术包括用于处理器芯片的电源管理的方法，其包括以下步骤。 为处理器芯片设置初始操作级别。 在预定的时间间隔之后，计算松弛。 如果松弛度大于零，则初始操作级别增加到下一级，否则保持初始操作级别。 在预定的时间间隔之后，重新计算松弛，并进一步包括累积的松弛。 如果重新计算的松弛大于零，则如果处理器芯片在初始操作电平下操作，则操作电平增加到下一个较高电平，否则如果处理器芯片为 在下一个更高的运行水平运行。 重新计算松弛的步骤，并将操作级别提高到下一级，或将操作级别恢复到初始操作级别。
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公开(公告)号：US20100058084A1
公开(公告)日：2010-03-04
申请号：US12201821
申请日：2008-08-29
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.
摘要翻译： 电源管理技术包括用于处理器芯片的电源管理的方法，其包括以下步骤。 为处理器芯片设置初始操作级别。 在预定的时间间隔之后，计算松弛。 如果松弛度大于零，则初始操作级别增加到下一级，否则保持初始操作级别。 在预定的时间间隔之后，重新计算松弛，并进一步包括累积的松弛。 如果重新计算的松弛大于零，则如果处理器芯片在初始操作电平下操作，则操作电平增加到下一个较高电平，否则如果处理器芯片为 在下一个更高的运行水平运行。 重新计算松弛的步骤，并将操作级别提高到下一级，或将操作级别恢复到初始操作级别。
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4.发明授权Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus 有权网络处理器系统芯片采用桥耦合协议，将多处理器宏核心局部总线转换为外设接口耦合系统总线公开(公告)号：US07412588B2
公开(公告)日：2008-08-12
申请号：US10768828
申请日：2004-01-30
IPC分类号： G06F15/16
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the SoC macro core. The process of protocol conversion contained within the SoC macro core does not require the processing resources of a host system. The system-on chip macro core includes a bridge device for coupling a local bus in the protocol converting multiprocessor SoC macro core local bus to peripheral interfaces coupled to a system bus.
摘要翻译： 网络处理器包括系统级芯片（SoC）宏核心，并且用作单芯片协议转换器，其接收根据第一协议类型生成的分组，并且处理分组以实现协议转换，并且生成用于输出的第二协议类型的转换分组 其协议转换过程完全在SoC宏核心内进行。 包含在SoC宏核心内的协议转换过程不需要主机系统的处理资源。 系统级芯片宏核心包括用于将协议转换多处理器SoC宏核心局部总线中的局部总线耦合到耦合到系统总线的外设接口的桥接器件。
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公开(公告)号：US20050021874A1
公开(公告)日：2005-01-27
申请号：US10768828
申请日：2004-01-30
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译： 一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行 在单个集成电路芯片内。 单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。 分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。 单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。
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公开(公告)号：US08811422B2
公开(公告)日：2014-08-19
申请号：US13269065
申请日：2011-10-07
IPC分类号： H04J3/16 , G06F15/167 , H04L12/56 , G06F15/78
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译： 一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行 在单一集成电路芯片内。 单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。 单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。
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公开(公告)号：US20120082171A1
公开(公告)日：2012-04-05
申请号：US13269065
申请日：2011-10-07
IPC分类号： H04L12/00
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译： 一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行 在单一集成电路芯片内。 单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。 单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。
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公开(公告)号：US20090059955A1
公开(公告)日：2009-03-05
申请号：US12189675
申请日：2008-08-11
IPC分类号： H04J3/22
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译： 一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行 在单个集成电路芯片内。 单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。 分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。 单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。
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公开(公告)号：US08036243B2
公开(公告)日：2011-10-11
申请号：US12189675
申请日：2008-08-11
IPC分类号： H04J3/16
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译： 一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行 在单个集成电路芯片内。 单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。 分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。 单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。
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