公开(公告)号：US5418953A

公开(公告)日：1995-05-23

申请号：US46028

申请日：1993-04-12

申请人： Peter D. Hunt ,  Jon K. Elliott ,  Richard J. Tobias ,  Alan J. Herring ,  Craig R. Morgan ,  John A. Hiller

发明人： Peter D. Hunt ,  Jon K. Elliott ,  Richard J. Tobias ,  Alan J. Herring ,  Craig R. Morgan ,  John A. Hiller

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F15/16 ,  G06F15/177 ,  G06F15/82 ,  G06F9/40

CPC分类号： G06F9/5066

摘要： A method is employed for pre-assignment and pre-scheduling of tasks that enables allocation across multiple physical processors arranged in a variety of architectures. The method comprises the steps of: constructing a DFG of tasks to be performed to provide a solution for a problem; determining cost values for each task and the overall problem, such cost values taking into account a target multiprocessor architecture and factors such as elapsed task execution times. The method pre-assigns the tasks to logical processors and assures that inter-dependent tasks are executable by logical processors that are within required communications delay criteria of each other. The assigning action attempts to arrive at a minimal cost value for all tasks comprising the problem. The pre-assigned tasks are then pre-scheduled based upon a performance criteria and are converted to machine code. The machine code is then deployed to physical processors in the target multi-processor architecture. The deploying action maps the logical processors' pre-assigned programs (comprising assigned tasks) onto physical processors, using data regarding the multi-processor architecture and the current utilization of the physical processors in the architecture, all while assuring that inter-dependent tasks are mapped so as to fulfill interprocessor communication delay criteria.

摘要翻译： 采用一种方法用于预先分配和预先安排任务，这些任务能够在多种结构中排列的多个物理处理器之间进行分配。 该方法包括以下步骤：构建要执行的任务的DFG以提供问题的解决方案; 确定每个任务的成本值和总体问题，考虑到目标多处理器架构以及诸如经过的任务执行时间之类的因素的这种成本值。 该方法将任务分配给逻辑处理器，并确保相互依赖的任务可由逻辑处理器执行，这些逻辑处理器在彼此所需的通信延迟标准之内。 分配动作尝试为包含该问题的所有任务达到最低成本值。 然后，预先分配的任务将根据性能标准进行预先安排，并转换为机器代码。 然后将机器代码部署到目标多处理器架构中的物理处理器。 部署动作使用关于多处理器架构的数据和架构中的物理处理器的当前利用率将逻辑处理器的预先分配的程序（包括分配的任务）映射到物理处理器上，同时确保相互依赖的任务是 映射以实现处理器间通信延迟标准。

公开(公告)号：US5210832A

公开(公告)日：1993-05-11

申请号：US725905

申请日：1991-07-03

申请人： Robert M. Maier ,  John C. Andoh ,  Arno S. Krakauer ,  Richard J. Tobias ,  Allan J. Zmyslowski

发明人： Robert M. Maier ,  John C. Andoh ,  Arno S. Krakauer ,  Richard J. Tobias ,  Allan J. Zmyslowski

IPC分类号： G06F9/318

CPC分类号： G06F9/3017

摘要： In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.

摘要翻译： 在具有域存储空间的用户域和具有仿真存储空间的仿真域的数据处理装置中，通过调用仿真域中的指令程序来模拟用户域中的指令。 连接以接收指令序列的指令寄存器被划分为多个字段。 指令寄存器的至少一个字段标识用于执行指令的操作数的地址信息的位置。 该指令被解码以产生控制码。 控制代码包括调用仿真程序的分支信号和域访问控制信号，以指示仿真程序是否需要访问用户域存储库以供执行。 在仿真程序的执行期间，由地址信息标识的位置暗示了域访问 - 一组已被预选为隐含域寻址的地址寄存器的位置。

公开(公告)号：US4851993A

公开(公告)日：1989-07-25

申请号：US41046

申请日：1987-04-20

申请人： Jack Chen ,  Jeffrey A. Thomas ,  Joseph A. Petolino, Jr. ,  Michael J. Begley ,  Ajay Shah ,  Michael D. Taylor ,  Richard J. Tobias

发明人： Jack Chen ,  Jeffrey A. Thomas ,  Joseph A. Petolino, Jr. ,  Michael J. Begley ,  Ajay Shah ,  Michael D. Taylor ,  Richard J. Tobias

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0888 ,  G06F9/3826

摘要： Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

摘要翻译： 将数据从主存储单元旁路到中间存储单元周围的指令和操作数处理单元，提高了数据处理系统的性能。 指令和操作数处理单元向中间存储单元或高速缓存提供对操作数的请求。 如果从缓存中缺少该行，则从主存储单元检索请求操作数。 旁路数据路径连接在主存储单元之前，在高速缓存中的错误检测装置之前，以及用于将请求的操作数直接传送到指令和操作数处理单元的指令和操作数处理单元。 控制，耦合以接收对操作数的请求以及指令和操作数处理单元的信号，指示和操作数处理单元在数据包括请求的操作数时从旁路数据路径接收所请求的操作数。

公开(公告)号：US4785392A

公开(公告)日：1988-11-15

申请号：US918491

申请日：1986-10-14

申请人： Robert M. Maier ,  John C. Andoh ,  Arno S. Krakauer ,  Richard J. Tobias ,  Allan J. Zmyslowski

发明人： Robert M. Maier ,  John C. Andoh ,  Arno S. Krakauer ,  Richard J. Tobias ,  Allan J. Zmyslowski

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/45579

摘要： In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.

摘要翻译： 在具有域存储空间的用户域和具有仿真存储空间的仿真域的数据处理装置中，通过调用仿真域中的指令程序来模拟用户域中的指令。 连接以接收指令序列的指令寄存器被划分为多个字段。 指令寄存器的至少一个字段标识用于执行指令的操作数的地址信息的位置。 该指令被解码以产生控制码。 控制代码包括调用仿真程序的分支信号和域访问控制信号，以指示仿真程序是否需要访问用户域存储库以供执行。 在仿真程序的执行期间，由地址信息标识的位置暗示了域访问 - 一组已被预选为隐含域寻址的地址寄存器的位置。

公开(公告)号：US5367701A

公开(公告)日：1994-11-22

申请号：US994122

申请日：1992-12-21

申请人： Mark von Gnechten ,  Brian T. Chase ,  Richard J. Tobias ,  David Dooley

发明人： Mark von Gnechten ,  Brian T. Chase ,  Richard J. Tobias ,  David Dooley

IPC分类号： G06F11/00 ,  G06F13/00

CPC分类号： G11C7/1075 ,  G11C29/74 ,  G06F11/004

摘要： A partitionable computing system includes main storage units on respective sides of the complex which can be fully controlled and accessible from either side. The system includes a dual port main storage unit design, and a system controller design capable of driving plural main storage unit interfaces. With this configuration, one system controller and the processors attached to that system controller can be taken offline and partitioned off to perform maintenance while all of the physical main storage units remain accessible to the processors on the surviving side of the complex. The operating system sees no loss available memory and the time to perform the maintenance activity is significantly reduced.

摘要翻译： 可分割计算系统包括在复合体的相应侧上的主存储单元，其可以从任一侧完全控制和访问。 该系统包括双端口主存储单元设计，以及能够驱动多个主存储单元接口的系统控制器设计。 通过这种配置，可以使一个系统控制器和连接到该系统控制器的处理器脱机并进行分区以进行维护，同时所有的物理主存储单元对复合体的存活侧的处理器保持可访问。 操作系统看不到可用内存丢失，执行维护活动的时间显着减少。