公开(公告)号：US20140071723A1

公开(公告)日：2014-03-13

申请号：US14026262

申请日：2013-09-13

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： H02M1/42

CPC分类号： H02M1/4208 ,  H02M1/4258 ,  H02M2001/0012 ,  Y02B70/126

摘要： The disclosed technology performs power factor correction involving rectifying and adjusting an input power supply signal with a PWM signal. The PWM signal is generated based on a closed feedback signal obtained from a load, as well as adjusted harmonic content retrieved from a sensed input power supply signal. The adjusted harmonic content is produced by extracting a fundamental signal and a plurality of harmonic signals from the sensed input power supply signal, modifying the plurality of harmonic signals by dividing by the fundamental signal, and combining the modified harmonic signals into a duty factor distortion signal. The duty factor distortion signal controls a duty factor of the PWM signal to provide a substantially square wave template. Furthermore, the power factor is increased by forcing the input power supply signal to follow the substantially square wave template.

摘要翻译： 所公开的技术执行功率因数校正，其涉及用PWM信号校正和调整输入电源信号。 基于从负载获得的闭合反馈信号产生PWM信号，以及从感测的输入电源信号检索的调整的谐波含量。 通过从所感测的输入电源信号中提取基本信号和多个谐波信号，通过除以基本信号来修正多个谐波信号，并将修正的谐波信号组合成占空系数失真信号来产生调整后的谐波含量 。 占空因数失真信号控制PWM信号的占空比，以提供基本上为方波的模板。 此外，通过强制输入电源信号跟随大致方波模板来增加功率因数。

公开(公告)号：US08018744B1

公开(公告)日：2011-09-13

申请号：US12779843

申请日：2010-05-13

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： H02M1/12 ,  G01R23/20 ,  H03K5/08

CPC分类号： G05F1/70 ,  Y02P80/112

摘要： A power factor correction circuit (42/44) responsive to an input power supply signal at an input supply voltage (VAC) that varies largely sinusoidally with time at a fundamental supply frequency contains regulator/control circuitry (60, 62, and 64) for measuring and removing overtones (ILDm or IFWRm) in the input supply current (ILD) or in a rectified form (IFWR) of the input supply current. Each overtone is expressible as the product of an amplitude component (Im) and a sinusoidal function (Im sin [(m+1)ωACt]) that varies with time at an integer multiple of the fundamental supply frequency. The regulator/control circuitry measures an overtone by determining the overtone's amplitude component. After generating an adjustment factor (SADJ) largely as the product of that overtone's amplitude component and an associated sinusoidal function, the regulator/control circuitry adjusts the input supply current or its rectified form by an amount corresponding to the adjustment factor for each measured overtone.

摘要翻译： 响应于输入电源电压（VAC）的输入电源信号的功率因数校正电路（42/44），其基本电源频率随着时间的变化很大程度地正弦变化，包括调节器/控制电路（60,62和64），用于 在输入电源电流（ILD）或整流形式（IFWR）中测量和去除输入电源电流的泛波（ILDm或IFWRm）。 每个泛音可以表示为幅度分量（Im）和正弦函数（Im sin [（m + 1）ωACt]）的乘积，其随着时间在基本供电频率的整数倍上变化。 调节器/控制电路通过确定泛音振幅分量来测量泛音。 在主要作为该泛音振幅分量和相关正弦函数的乘积产生调整因子（SADJ）之后，调节器/控制电路将输入电源电流或其整流形式调整为与每个测量的泛音相应的调整因子的量。

公开(公告)号：US4701883A

公开(公告)日：1987-10-20

申请号：US875909

申请日：1986-06-19

申请人： Robert S. Wrathall ,  Kevin L. McLaughlin

发明人： Robert S. Wrathall ,  Kevin L. McLaughlin

IPC分类号： G11C8/16 ,  G11C11/411 ,  G11C11/40

CPC分类号： G11C11/4116 ,  G11C8/16

摘要： A CMOS memory cell is provided having separate read and write bit lines and coupling devices associated therewith which provide improved read and write times for the cell. The separate read line is coupled to the cell via a bipolar transistor which supplies increased drive current to the read bit line thereby decreasing the read time. The separate write line is coupled to the cell via a low impedance diode which reduces the write time.

摘要翻译： 提供具有分离的读取和写入位线和与之相关联的耦合器件的CMOS存储器单元，其为该单元提供改进的读取和写入时间。 单独的读取线通过双极晶体管耦合到单元，该双极晶体管将增加的驱动电流提供给读取位线，从而减少读取时间。 单独的写入线通过低阻抗二极管耦合到单元，这降低了写入时间。

公开(公告)号：US11637493B2

公开(公告)日：2023-04-25

申请号：US17589425

申请日：2022-01-31

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： H02M1/42 ,  H02M1/12 ,  H02M5/293 ,  H02M1/00

摘要： Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

公开(公告)号：US10998815B1

公开(公告)日：2021-05-04

申请号：US17102035

申请日：2020-11-23

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： H02M1/42 ,  H02M1/12 ,  H02M5/293 ,  H02M1/00

摘要： Provided are electrical circuits and methods for power factor correction. An example method includes receiving, by converter, an input voltage at a fundamental frequency and generating an output voltage; generating, based on the output voltage, a first measurement signal; subtracting a first reference signal from the first measurement signal to obtain a first error signal; generating an adaptive current sense signal, generating a reference voltage based on the input voltage, subtracting the reference voltage from the current sense signal thus generating a second measurement signal to control the current measurement; subtracting the second measurement signal from the input voltage to obtain a difference signal, wherein the difference signal is largely minimized by removing overtones of the fundamental frequency; generating, based on the difference signal, a second error signal; using a sum of the second error signal as a first order correction to the first error signal to regulate the converter.

公开(公告)号：US06737841B2

公开(公告)日：2004-05-18

申请号：US10210514

申请日：2002-07-31

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： G05F140

CPC分类号： H02M3/156

摘要： A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier with capacitive feedback and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is an intermediate node between two gain stages of a second circuit in the first circuit. The capacitive feedback can be formed by a third capacitor coupled in parallel with one or more of the gain stages in the amplifier. In operation, the capacitance of the second capacitor and an input impedance of the second gain stage of the second circuit introduce a zero in the closed loop feedback system at the third node. The compensation circuit can be applied to a switching regulator controller for adding a zero in the feedback system of a switching regulator.

摘要翻译： 在闭环反馈系统中并入的第一电路中引入零的补偿电路包括在第一电路中的输入节点和求和节点之间串联连接的第一电容器，具有电容反馈的放大器和第二电容器。 在一个实施例中，求和节点是第一电路中第二电路的两个增益级之间的中间节点。 电容反馈可以由与放大器中的一个或多个增益级并联耦合的第三电容器形成。 在操作中，第二电容器的电容和第二电路的第二增益级的输入阻抗在第三节点处的闭环反馈系统中引入零。 补偿电路可以应用于开关稳压器控制器，用于在开关稳压器的反馈系统中增加零。

公开(公告)号：US06724257B2

公开(公告)日：2004-04-20

申请号：US10210696

申请日：2002-07-31

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： H03F345

CPC分类号： H02M3/156

摘要： An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascode gain stage and generates a third output signal. The cascode gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.

摘要翻译： 误差放大器电路包括具有共源共栅增益级的差分放大器和放大器。 差分放大器接收第一输入信号和第二输入信号，并在表示第一输入信号和第二输入信号之间的差的输出端产生输出信号。 串联增益级被耦合以接收差分放大器的输出信号并产生第二输出信号。 共源共栅增益级由电流镜产生的偏置电流偏置。 放大器接收来自级联增益级的第二输出信号并产生第三输出信号。 共源共栅增益级被控制信号偏置，使得所述电流镜产生与第一输入信号和第二输入信号的电压差的变化基本恒定的偏置电流。

公开(公告)号：US6002244A

公开(公告)日：1999-12-14

申请号：US193659

申请日：1998-11-17

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： G01K7/01 ,  G05F3/26 ,  G05F3/30 ,  G05F3/20

CPC分类号： G05F3/30 ,  G01K7/01 ,  G05F3/267 ,  Y10S323/907

摘要： A temperature monitoring circuit with thermal hysteresis in CMOS circuitry utilizes bipolar transistors which are parasitic to standard CMOS circuitry. A concept of band-gap circuitry is used to provide a proportional to absolute temperature (PTAT) current, which is used as a reference. An output signal is produced above a predetermined temperature by comparing current changes between the PTAT current and a PTAT controlled current in a single current path. The PTAT controlled current decreases faster with temperature increase than the change in the PTAT current. The thermal hysteresis is accomplished by inverting the output signal to control a hysteresis transistor for selectively shorting out a hysteresis resistor. In the preferred embodiment, a start circuit is attached to the temperature monitoring circuit with thermal hysteresis to provide an initial current to activate the present invention. The start circuit is quickly shorted out once the devices of the present invention are turned on.

摘要翻译： CMOS电路中具有热滞后的温度监控电路利用寄生于标准CMOS电路的双极型晶体管。 使用带隙电路的概念来提供与绝对温度（PTAT）电流成正比的参数。 通过比较单个电流路径中的PTAT电流和PTAT控制电流之间的电流变化，在预定温度以上产生输出信号。 随PTAT电流的变化，PTAT控制电流随着温度的升高而下降得更快。 热滞后是通过反相输出信号来控制滞回晶体管来选择性地短路迟滞电阻。 在优选实施例中，启动电路被附加到具有热滞后的温度监控电路，以提供初始电流来激活本发明。 一旦本发明的装置被接通，起动电路就快速地短路。

公开(公告)号：US5164802A

公开(公告)日：1992-11-17

申请号：US672243

申请日：1991-03-20

申请人： Frederick P. Jones ,  Joseph A. Yedinak ,  John M. S. Neilson ,  Robert S. Wrathall ,  Jeffrey G. Mansmann ,  Claire E. Jackoski

发明人： Frederick P. Jones ,  Joseph A. Yedinak ,  John M. S. Neilson ,  Robert S. Wrathall ,  Jeffrey G. Mansmann ,  Claire E. Jackoski

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7803 ,  H01L29/7806 ,  H01L29/7839

摘要： A monolithic semiconductor device comprises a VDMOS transistor having first and second main electrodes and a control electrode, and a lateral MOSFET having first and second main electrodes and a control electrode, wherein one of the first and second electrodes of the lateral MOSFET has a lower doping concentration than that of the first and second main electrodes of the VDMOS transistor for forming a Schottky barrier diode.

公开(公告)号：US4380706A

公开(公告)日：1983-04-19

申请号：US219797

申请日：1980-12-24

申请人： Robert S. Wrathall

发明人： Robert S. Wrathall

IPC分类号： G05F3/30 ,  H03K3/26 ,  H03K3/01

CPC分类号： G05F3/30

摘要： A voltage reference source is provided which is temperature stable and can be made by standard CMOS processes. The voltage reference can provide an output voltage which is equal to twice the bandgap voltage. The voltage reference circuit uses a differential amplifier which has an output coupled to an additional amplifying stage. Two substrate bipolar transistors are used wherein the emitter current density of one of the transistors is larger than the emitter current density of the other transistor. An additional transistor is inserted between the output of the amplifying stage and the substrate bipolar transistors thereby providing the output voltage of twice the bandgap voltage.

摘要翻译： 提供了一种温度稳定的电压参考源，可以通过标准CMOS工艺制造。 电压基准可以提供等于带隙电压两倍的输出电压。 电压参考电路使用具有耦合到附加放大级的输出的差分放大器。 使用两个基板双极晶体管，其中一个晶体管的发射极电流密度大于另一个晶体管的发射极电流密度。 在放大级的输出端和基板双极型晶体管之间插入另外的晶体管，从而提供两倍于带隙电压的输出电压。