公开(公告)号：US07915056B2

公开(公告)日：2011-03-29

申请号：US12051868

申请日：2008-03-20

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC: G01R31/26

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US20080126061A1

公开(公告)日：2008-05-29

申请号：US11464014

申请日：2006-08-11

Applicant: Jerry D. Hayes ,  Sambasivan Narayan ,  Jeffery H. Oppold ,  James E. Sundquist

Inventor： Jerry D. Hayes ,  Sambasivan Narayan ,  Jeffery H. Oppold ,  James E. Sundquist

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.

Abstract translation: 本发明的实施例提供了用于分析技术的方法，计算机程序产品等，以减少模拟以表征晶体管电路中的变化的影响。 在集成电路中模拟晶体管的方法通过将一组并联晶体管减少到单个等效晶体管来开始。 随后模拟等效晶体管，其中仅模拟一部分并联晶体管。 接下来，将集成电路分为通道连接部件，并对通道连接部件进行仿真。 为每种类型的通道连接组件创建一个表格; 并且通过集成电路仿真的结果计算跨芯片变化方程的参数化。 此外，创建表条目，其包括多个晶体管类型，多个独特的晶体管原始图案和/或通过晶体管基元图案中的每一个的路径的数量。

公开(公告)号：US20090237103A1

公开(公告)日：2009-09-24

申请号：US12051868

申请日：2008-03-20

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC: G01R31/26 ,  H01L23/00 ,  G06F17/50

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US20080201676A1

公开(公告)日：2008-08-21

申请号：US12114203

申请日：2008-05-02

Applicant: Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

Inventor： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract translation: 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。

公开(公告)号：US20070234256A1

公开(公告)日：2007-10-04

申请号：US11762405

申请日：2007-06-13

Applicant: HONGLIANG CHANG ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

Inventor： HONGLIANG CHANG ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract translation: 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。

公开(公告)号：US07293248B2

公开(公告)日：2007-11-06

申请号：US11056850

申请日：2005-02-11

Applicant: Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

Inventor： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5031

Abstract: There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.

Abstract translation: 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。

公开(公告)号：US20060085775A1

公开(公告)日：2006-04-20

申请号：US11056850

申请日：2005-02-11

Applicant: Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

Inventor： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5031

Abstract: There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.

Abstract translation: 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。

公开(公告)号：US08015525B2

公开(公告)日：2011-09-06

申请号：US12114203

申请日：2008-05-02

Applicant: Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

Inventor： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract translation: 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。