公开(公告)号：US07424315B2

公开(公告)日：2008-09-09

申请号：US10499401

申请日：2002-12-10

申请人： Patrick Willem Hubert Heuts ,  Hendrik Boezen ,  Harm Gerwin Joan Voss ,  Stefan Gerhard Erich Butselaar

发明人： Patrick Willem Hubert Heuts ,  Hendrik Boezen ,  Harm Gerwin Joan Voss ,  Stefan Gerhard Erich Butselaar

IPC分类号： H04B1/38 ,  H04B7/00 ,  H04B1/16 ,  H04B1/04 ,  H04B3/36 ,  G08C17/00

CPC分类号： G06F1/3253 ,  G06F1/3203 ,  Y02D10/151

摘要： The communication bus system comprises a plurality of node circuits (10a-d) and a relay circuit (12, 14, 16) coupling the node circuits (10a-d). The relay circuit (12, 14, 16) has a transceiver circuit (124, 164) for relaying messages (21) between the node circuits (10a-d) in a normal mode. The transceiver circuit (124, 164) is powered down in a sleep mode. A detector circuit (120, 160) detects an incoming message (41) when the relay circuit (12, 14, 16) is in a sleep mode. A mode control circuit (122, 162) powers up the transceiver (124, 164) in response to detection of an incoming message (21). Steps are taken that ensure, in the normal mode, that messages (21) will not be relayed in unreadable form. The mode control circuit (122, 162) is arranged to cause the transceiver (124, 164) to relay a remainder (25) of the incoming message (21) after power up. In an embodiment the power needed to transmit the remainder (25) of the message (21) is drained from a capacitor (306) in the power supply (30) before the power supply (30) controls the power supply voltage in the normal mode. In another embodiment the detector circuit (120, 160) temporarily controls the direction of operation of the transceivers (124, 164) at the start of the normal mode instead of further detectors (58a-d) that normally control the direction of operation in the normal mode.

摘要翻译： 通信总线系统包括耦合节点电路（10a-d）的多个节点电路（10a-d）和继电器电路（12,14,16）。 继电器电路（12,14,16）具有用于以正常模式中继节点电路（10a-d）之间的消息（21）的收发器电路（124,164）。 在休眠模式下，收发器电路（124,164）被掉电。 当继电器电路（12,14,16）处于睡眠模式时，检测器电路（120,160）检测输入消息（41）。 模式控制电路（122,162）响应于输入消息（21）的检测，对收发器（124,164）供电。 采取步骤，确保在正常模式下，消息（21）将不会以不可读的形式进行中继。 模式控制电路（122,162）被布置成使得收发器（124,164）在上电之后中继输入消息（21）的余数（25）。 在一个实施例中，在电源（30）以正常模式控制电源电压之前，将消息（21）的剩余部分（25）所需的功率从电源（30）中的电容器（306）中排出 。 在另一个实施例中，检测器电路（120,160）在正常模式开始时临时控制收发器（124,164）的操作方向，而不是通常控制正常操作方向的另外的检测器（58 ad） 模式。

公开(公告)号：US07191348B2

公开(公告)日：2007-03-13

申请号：US10525579

申请日：2003-07-22

申请人： Clemens Gerhardus Johannes De Haas ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Clemens Gerhardus Johannes De Haas ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： G06F1/26

CPC分类号： G06F1/24 ,  H03K5/04 ,  H03K5/08 ,  H03K5/1252

摘要： An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses. By using a diode instead of a switching transistor the circuit is more robust against the effect of interfering pulses.

摘要翻译： 集成电路具有用于连接外部信号导体的输入连接，该外部信号导体通过信号以执行装置中的功能。 外部信号导体可以拾取高频内容的强干扰信号，例如当该装置用于汽车时。 为了防止意外执行功能，该设备包含定时器电路，该定时器电路包括耦合到集成节点的电容和电流供应电路。 放电二极管耦合在输入连接和积分节点之间，其极性使得放电二极管在正向偏压时能够从电流供应电路引出电流。 检测器耦合到积分节点，用于产生要提供给集成电路器件的信号以响应导体上的信号转变。 在检测器检测到短脉冲情况下的转换之前，二极管用于复位积分节点上的积分。 通过使用二极管代替开关晶体管，该电路相对于干扰脉冲的影响更为鲁棒。

公开(公告)号：US08368432B2

公开(公告)日：2013-02-05

申请号：US12945248

申请日：2010-11-12

申请人： Stefan Gerhard Erich Butselaar ,  Louk Boomkamp ,  Cornelis Klaas Waardenburg ,  Ben Gelissen ,  Mehdi El-Ghorba

发明人： Stefan Gerhard Erich Butselaar ,  Louk Boomkamp ,  Cornelis Klaas Waardenburg ,  Ben Gelissen ,  Mehdi El-Ghorba

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H04L25/028 ,  H04L25/08

摘要： An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.

摘要翻译： 提供了一个抗干扰发射机。 根据各种示例性实施例，发射机电路包括控制电路，该控制电路被配置为将目标电平（例如，范围）上的来自相应的高侧电流源和低侧电流源的负载保持为电流之和。 在一些应用中，钳位电路用于分别根据负载的低侧和高侧的变化将电流钳位到负载的高低侧。

公开(公告)号：US07532046B2

公开(公告)日：2009-05-12

申请号：US11632031

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H03B1/00

CPC分类号： H04L25/0296 ,  H03F3/45991 ,  H03F2203/45538 ,  H03F2203/45588 ,  H03F2203/45616 ,  H04L25/0274

摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.

摘要翻译： 本发明涉及一种具有开关控制逻辑（151）的差分总线的接收器，其具有两个具有电阻元件（7,61。，70,8和5,11，...，20,6）的分支以及开关（ 3，80），用于切换电阻元件，其中开关控制逻辑将开关置于用于通过向总线施加共模电压来确定总线上的信号的绝对电平的第一例程中，通过比较 具有参考电压的第一电阻分支，通过选择正确的开关设置，以及将这些设置写入内部存储装置，以及在第二程序中，通过向总线施加共模电压来最小化两个电阻分支之间的失配 通过比较第二电阻分支的电压与已修整的第一电阻分支的电压，通过选择第二分支的正确开关设置，并将这些设置写入内部存储装置。 因此，接收机提供良好的平衡和共模抑制。

公开(公告)号：US08189691B2

公开(公告)日：2012-05-29

申请号：US11632028

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H04L25/00

CPC分类号： G06F13/4072 ,  H03F2203/7203 ,  H04L25/0272 ,  H04L25/0292

摘要： The invention relates to a receiver for a differential data bus with two resistive branches (1, 2, 3; 4, 5, 6), with a differential amplifier with two transistors (9, 10), with a resistor (13), and with a control logic (16) that controls a switch (15) with which a current from a current source (14) is switchable to either side of the resistor (13), which resistor couples the two transistors (9, 10), and with two operational amplifiers (17, 18) which are coupled to the two transistors (9,10) of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers (17,18) whether a “0” or a “1” is expected on the bus and which receiver sets the switch (25) accordingly so that a comparison with the received bus signal is made.

摘要翻译： 本发明涉及一种具有两个电阻分支（1,2,3,4,5,6）的差分数据总线的接收机，具有带有电阻器（13）的具有两个晶体管（9,10）的差分放大器，以及 控制逻辑（16），其控制开关（15），来自电流源（14）的电流可通过该开关（15）切换到电阻器（13）的任一侧，哪个电阻器耦合两个晶体管（9,10），以及 其中两个运算放大器（17,18）耦合到具有相反极点的差分放大器的两个晶体管（9,10），其中控制逻辑从两个运算放大器（17,18）的输出信号中检测出， 在总线上是否期望“0”或“1”，并且相应地接收器设置开关（25），使得与所接收的总线信号进行比较。

公开(公告)号：US20120119793A1

公开(公告)日：2012-05-17

申请号：US12945248

申请日：2010-11-12

申请人： Stefan Gerhard Erich Butselaar ,  Louk Boomkamp ,  Cornelis Klaas Waardenburg ,  Ben Gelissen ,  Mehdi El-Ghorba

发明人： Stefan Gerhard Erich Butselaar ,  Louk Boomkamp ,  Cornelis Klaas Waardenburg ,  Ben Gelissen ,  Mehdi El-Ghorba

IPC分类号： H03K3/00

CPC分类号： H04L25/028 ,  H04L25/08

摘要： An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.

摘要翻译： 提供了一个抗干扰发射机。 根据各种示例性实施例，发射机电路包括控制电路，该控制电路被配置为将目标电平（例如，范围）上的来自相应的高侧电流源和低侧电流源的负载保持为电流之和。 在一些应用中，钳位电路用于分别根据负载的低侧和高侧的变化将电流钳位到负载的高低侧。

公开(公告)号：US20110188606A1

公开(公告)日：2011-08-04

申请号：US11632028

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H04L27/00

CPC分类号： G06F13/4072 ,  H03F2203/7203 ,  H04L25/0272 ,  H04L25/0292

摘要： The invention relates to a receiver for a differential data bus with two resistive branches (1, 2,3; 4, 5, 6), with a differential amplifier with two transistors (9, 10), with a resistor (13), and with a control logic (16) that controls a switch (15) with which a current from a current source (14) is switchable to either side of the resistor (13), which resistor couples the two transistors (9, 10), and with two operational amplifiers (17, 18) which are coupled to the two transistors (9,10) of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers (17,18) whether a “0” or a “1” is expected on the bus and which receiver sets the switch (25) accordingly so that a comparison with the received bus signal is made.

摘要翻译： 本发明涉及一种具有两个电阻分支（1,2,3,4,5,6）的差分数据总线的接收机，具有带有电阻器（13）的具有两个晶体管（9,10）的差分放大器，以及 控制逻辑（16），其控制开关（15），来自电流源（14）的电流可通过该开关（15）切换到电阻器（13）的任一侧，哪个电阻器耦合两个晶体管（9,10），以及 其中两个运算放大器（17,18）耦合到具有相反极点的差分放大器的两个晶体管（9,10），其中控制逻辑从两个运算放大器（17,18）的输出信号中检测出， 在总线上是否期望“0”或“1”，并且相应地接收器设置开关（25），使得与所接收的总线信号进行比较。

公开(公告)号：US20080265969A1

公开(公告)日：2008-10-30

申请号：US11632031

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H03L5/00

CPC分类号： H04L25/0296 ,  H03F3/45991 ,  H03F2203/45538 ,  H03F2203/45588 ,  H03F2203/45616 ,  H04L25/0274

摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, —and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.

摘要翻译： 本发明涉及一种具有开关控制逻辑（151）的差分总线的接收器，其具有两个具有电阻元件（7,61。，70,8和5,11，...，20,6）的分支以及开关（ 3，80），用于切换电阻元件，其中开关控制逻辑将开关设置在第一程序中，用于通过对总线施加共模电压来确定总线上的信号的绝对电平，通过比较 具有参考电压的第一电阻分支，通过选择正确的开关设置，以及将这些设置写入内部存储装置，以及在第二程序中，通过向总线施加共模电压来最小化两个电阻分支之间的失配 通过比较第二电阻分支的电压与已修整的第一电阻分支的电压，通过选择第二分支的正确开关设置，并将这些设置写入内部存储装置。 因此，接收机提供良好的平衡和共模抑制。

公开(公告)号：US07095751B2

公开(公告)日：2006-08-22

申请号：US10095398

申请日：2002-03-11

申请人： Hendrik Boezen ,  Stefan Gerhard Erich Butselaar ,  Harm Gerwin Joan Voss

发明人： Hendrik Boezen ,  Stefan Gerhard Erich Butselaar ,  Harm Gerwin Joan Voss

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L12/44

摘要： In a network a star node (SN1) interconnects a plurality of stations (ST1–ST3). The star node (SN1) has interfaces (I1–I3), each having a connection terminal (BP) for connecting a selected one of the stations to the star node (SN1) and each interface receives at a connection terminal (BP) a signal from the station associated with that interface and forwards the received signal to the connection terminal (BP) of the other interfaces. The star node (SN1) further has a common terminal (RT1) and each interface has a receiver (CMP1) coupled to the connection terminal (BP) for receiving the signal from the associated station, a transmitter (TR) coupled to the connection terminal (BP), a first activity detector (A1) for generating a first activity signal (AS1) in response to signal transitions at an input (CIP1) of the receiver (CMP1), a second activity detector (A2) for generating a second activity signal (AS2) in response to signal transitions at the common terminal (RT1), a first switch (SW1) for disabling signal transfer from the receiver (CMP1) to the common terminal (RT1) in response to the second activity signal (AS2), and a second switch (SW2) for disabling signal transfer from the common terminal (RT1) to the transmitter (TR) in response to the first activity signal (AS1). The structure of the interface allows easy expansion of the number of interfaces within the star node (SN1) and a data protocol without a preamble.

摘要翻译： 在网络中，星形节点（SN 1）互连多个站（ST 1 -ST 3）。 星型节点（SN 1）具有接口（I 1 -I 3），每个接口具有连接端子（BP），用于将所选择的一个站点连接到星形节点（SN 1），并且每个接口在连接终端 BP）来自与该接口相关联的站的信号，并将接收到的信号转发到其他接口的连接终端（BP）。 星形节点（SN 1）还具有公共终端（RT 1），并且每个接口具有耦合到连接终端（BP）的接收机（CMP 1），用于从相关联的站接收信号;发射机（TR），耦合到 连接端子（BP），用于响应于接收器（CMP1）的输入端（CIP1）处的信号转换而产生第一活动信号（AS 1）的第一活动检测器（A 1），第二活动检测器 A 2），用于响应于公共端（RT 1）处的信号转换而产生第二活动信号（AS 2），用于禁止从接收机（CMP 1）到公共终端（CMP1）的信号传输的第一开关（SW 1） 响应于第二活动信号（AS 2）的第二开关（SW 2）和用于响应于第一活动信号（AS）而禁用从公共端（RT 1）到发射器（TR）的信号传输的第二开关（SW 2） 1）。 接口的结构允许容易地扩展星形节点（SN 1）内的接口数量和无前导码的数据协议。