公开(公告)号：US20090265449A1

公开(公告)日：2009-10-22

申请号：US12427615

申请日：2009-04-21

申请人： Nagendra Krishnappa ,  Sudhindra Prasad

发明人： Nagendra Krishnappa ,  Sudhindra Prasad

IPC分类号： G06F15/177 ,  G06F15/173

CPC分类号： G06F9/5061 ,  G06F2209/505 ,  H04L29/12254 ,  H04L29/12783 ,  H04L61/2038 ,  H04L61/35

摘要： A method for clustering comprising acquiring the required number of nodes for cluster formation based on node selection criteria; electing a cluster coordinator; and assigning the packages on the member nodes. The cluster coordinator is elected based on the mean time between failures value of the member nodes which may be calculated with the help of a diagnostic tool by logging the failure instances of the member nodes.

摘要翻译： 一种用于聚类的方法，包括：基于节点选择标准获取用于聚类形成的所需数量的节点; 选举一个集群协调员; 并将组件分配给成员节点。 基于可以通过记录成员节点的故障实例在诊断工具的帮助下计算的成员节点的故障值之间的平均时间来选出集群协调器。

公开(公告)号：US07349254B2

公开(公告)日：2008-03-25

申请号：US11444289

申请日：2006-05-31

申请人： Tholasampatti Subramanian Sudhindra Prasad

发明人： Tholasampatti Subramanian Sudhindra Prasad

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3427 ,  G11C16/3431

摘要： A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each memory cell is adapted to trap an amount of charge indicative of a programming state. A control circuit is operationally connected to the array and is adapted to access a memory cell of the array by means of storing charge in or removing charge from the memory cell. A disturb detection circuit is operationally connected to the array or the control circuit and is adapted to detect a disturbance level of the first sector based on a disturbance caused by accessing at least one memory cell of the second sector. A disturb leveling circuit is operationally connected to the array and the disturb detection circuit and is adapted to backup the programming state of memory cells of the first sector if the detected disturbance level exceeds a predefined threshold.

摘要翻译： 电荷捕获存储器件包括非易失性存储器单元阵列。 阵列至少具有第一扇区和第二扇区。 每个扇区包括多个存储单元。 每个存储器单元适于捕获指示编程状态的电荷量。 控制电路可操作地连接到阵列，并且适于通过存储电荷或从存储器单元中去除电荷来访问阵列的存储单元。 干扰检测电路可操作地连接到阵列或控制电路，并且适于基于由访问第二扇区的至少一个存储器单元而引起的干扰来检测第一扇区的干扰电平。 干扰均衡电路可操作地连接到阵列和干扰检测电路，并且如果检测到的干扰电平超过预定阈值，则适于备份第一扇区的存储器单元的编程状态。

公开(公告)号：US20070280002A1

公开(公告)日：2007-12-06

申请号：US11444289

申请日：2006-05-31

申请人： Tholasampatti Subramanian Sudhindra Prasad

发明人： Tholasampatti Subramanian Sudhindra Prasad

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427 ,  G11C16/3431

摘要： A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each memory cell is adapted to trap an amount of charge indicative of a programming state. A control circuit is operationally connected to the array and is adapted to access a memory cell of the array by means of storing charge in or removing charge from the memory cell. A disturb detection circuit is operationally connected to the array or the control circuit and is adapted to detect a disturbance level of the first sector based on a disturbance caused by accessing at least one memory cell of the second sector. A disturb leveling circuit is operationally connected to the array and the disturb detection circuit and is adapted to backup the programming state of memory cells of the first sector if the detected disturbance level exceeds a predefined threshold.

摘要翻译： 电荷捕获存储器件包括非易失性存储器单元阵列。 阵列至少具有第一扇区和第二扇区。 每个扇区包括多个存储单元。 每个存储器单元适于捕获指示编程状态的电荷量。 控制电路可操作地连接到阵列，并且适于通过存储电荷或从存储器单元中去除电荷来访问阵列的存储单元。 干扰检测电路可操作地连接到阵列或控制电路，并且适于基于由访问第二扇区的至少一个存储器单元而引起的干扰来检测第一扇区的干扰电平。 干扰均衡电路可操作地连接到阵列和干扰检测电路，并且如果检测到的干扰电平超过预定阈值，则其适于备份第一扇区的存储器单元的编程状态。

公开(公告)号：US20090154264A1

公开(公告)日：2009-06-18

申请号：US11955278

申请日：2007-12-12

申请人： Andreas Kux ,  Detlev Richter ,  Gert Koebernick ,  Juergen Engelhardt ,  Sudhindra Prasad

发明人： Andreas Kux ,  Detlev Richter ,  Gert Koebernick ,  Juergen Engelhardt ,  Sudhindra Prasad

IPC分类号： G11C7/00

CPC分类号： G11C16/349 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495

摘要： In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

公开(公告)号：US20080279004A1

公开(公告)日：2008-11-13

申请号：US12035837

申请日：2008-02-22

申请人： Tholasampatti Subramanian Sudhindra Prasad

发明人： Tholasampatti Subramanian Sudhindra Prasad

IPC分类号： G11C16/06 ,  G11C29/00

CPC分类号： G11C16/3418 ,  G11C16/3427 ,  G11C16/3431

摘要： A method for leveling bit errors in a charge-trapping memory device is disclosed. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused by accessing memory cells of the second sector. Data stored in the first sector is backed up if the validating indicates a likelihood of a forthcoming failure in the first sector.

摘要翻译： 公开了一种用于调整电荷俘获存储器件中的位错误的方法。 存储器件具有第一和第二扇区的存储器单元。 第一扇区通过计数在第一扇区的存储器单元中发生的位数失败，由访问第二扇区的存储器单元引起的位故障来验证。 如果验证指示在第一扇区中即将发生故障的可能性，则备份存储在第一扇区中的数据。

公开(公告)号：US07583532B2

公开(公告)日：2009-09-01

申请号：US12035837

申请日：2008-02-22

申请人： Tholasampatti Subramanian Sudhindra Prasad

发明人： Tholasampatti Subramanian Sudhindra Prasad

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/3427 ,  G11C16/3431

摘要： A method for leveling bit errors in a charge-trapping memory device is included. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused by accessing memory cells of the second sector. Data stored in the first sector is backed up if the validating indicates a likelihood of a forthcoming failure in the first sector.

摘要翻译： 包括用于调整电荷俘获存储器件中的位错误的方法。 存储器件具有第一和第二扇区的存储器单元。 第一扇区通过计数在第一扇区的存储器单元中发生的位数失败，由访问第二扇区的存储器单元引起的位故障来验证。 如果验证指示在第一扇区中即将发生故障的可能性，则备份存储在第一扇区中的数据。

公开(公告)号：US07636258B2

公开(公告)日：2009-12-22

申请号：US11955278

申请日：2007-12-12

申请人： Andreas Kux ,  Detlev Richter ,  Gert Koebernick ,  Juergen Engelhardt ,  Sudhindra Prasad

发明人： Andreas Kux ,  Detlev Richter ,  Gert Koebernick ,  Juergen Engelhardt ,  Sudhindra Prasad

IPC分类号： G11C16/00

CPC分类号： G11C16/349 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495

摘要： In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

摘要翻译： 根据本发明的实施例，提供了集成电路，存储器控制器，用于确定用于编程或擦除存储器段的电平的方法，以及用于确定存储器段的磨损等级得分的方法。 在本发明的实施例中，提供了一种用于确定用于编程或擦除存储器段的电平的方法，其中用于编程或擦除存储器段的第一电平被确定为初始编程/擦除电平的函数。 此外，对于存储器段的随后的编程/擦除操作确定第一更新级别，并且使用第一级确定用于在编程或擦除存储器段之后编程或擦除存储器段的第二级，其中第二级是 确定为第一更新水平的函数。