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    Integrated circuits, memory controller, and memory modules
    2.
    发明授权
    Integrated circuits, memory controller, and memory modules 失效
    集成电路，存储器控制器和存储器模块

    公开(公告)号：US07636258B2

    公开(公告)日：2009-12-22

    申请号：US11955278

    申请日：2007-12-12

    申请人： Andreas Kux ,  Detlev Richter ,  Gert Koebernick ,  Juergen Engelhardt ,  Sudhindra Prasad

    发明人： Andreas Kux ,  Detlev Richter ,  Gert Koebernick ,  Juergen Engelhardt ,  Sudhindra Prasad

    IPC分类号： G11C16/00

    CPC分类号： G11C16/349 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495

    摘要： In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

    摘要翻译： 根据本发明的实施例，提供了集成电路，存储器控制器，用于确定用于编程或擦除存储器段的电平的方法，以及用于确定存储器段的磨损等级得分的方法。 在本发明的实施例中，提供了一种用于确定用于编程或擦除存储器段的电平的方法，其中用于编程或擦除存储器段的第一电平被确定为初始编程/擦除电平的函数。 此外，对于存储器段的随后的编程/擦除操作确定第一更新级别，并且使用第一级确定用于在编程或擦除存储器段之后编程或擦除存储器段的第二级，其中第二级是 确定为第一更新水平的函数。

    Memory device and method for verifying information stored in memory cells
    4.
    发明申请
    Memory device and method for verifying information stored in memory cells 有权

    公开(公告)号：US20080019187A1

    公开(公告)日：2008-01-24

    申请号：US11489702

    申请日：2006-07-19

    申请人： Andreas Kux ,  Detlev Richter

    发明人： Andreas Kux ,  Detlev Richter

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/344 ,  G11C16/3445

    摘要： A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.

    Memory device with adaptive sense unit and method of reading a cell array
    5.
    发明授权
    Memory device with adaptive sense unit and method of reading a cell array 有权
    具有自适应感测单元的存储器件和读取单元阵列的方法

    公开(公告)号：US07489563B2

    公开(公告)日：2009-02-10

    申请号：US11668753

    申请日：2007-01-30

    申请人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Köbernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-André Löhr ,  Sören Irmer

    发明人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Köbernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-André Löhr ,  Sören Irmer

    IPC分类号： G11C7/00

    CPC分类号： G11C16/10 ,  G11C16/26

    摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

    摘要翻译： 提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。 平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。 通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。 通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而 增强存储设备的可靠性。

    Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array
    6.
    发明申请
    Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array 有权
    具有自适应感知单元的存储器件和读取单元阵列的方法

    公开(公告)号：US20080181012A1

    公开(公告)日：2008-07-31

    申请号：US11668753

    申请日：2007-01-30

    申请人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Kobernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-Andre Lohr ,  Soren Irmer

    发明人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Kobernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-Andre Lohr ,  Soren Irmer

    IPC分类号： G11C16/26

    CPC分类号： G11C16/10 ,  G11C16/26

    摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

    摘要翻译： 提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。 平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。 通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。 通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而 增强存储设备的可靠性。

    Method of operating an integrated circuit having at least one memory cell
    7.
    发明授权
    Method of operating an integrated circuit having at least one memory cell 失效
    操作具有至少一个存储单元的集成电路的方法

    公开(公告)号：US07688634B2

    公开(公告)日：2010-03-30

    申请号：US11834612

    申请日：2007-08-06

    申请人： Detlev Richter ,  Andreas Kux

    发明人： Detlev Richter ,  Andreas Kux

    IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C16/04 ,  G11C7/02

    CPC分类号： G11C16/10 ,  G11C16/28

    摘要： Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state.

    摘要翻译： 本发明的实施例一般涉及一种用于写入集成电路的至少一个存储单元的方法; 一种用于写入集成电路的至少两个存储单元的方法; 和集成电路。 在本发明的实施例中，提供了一种用于写入集成电路的至少一个存储单元的方法。 该方法包括根据至少一个参考存储器单元的写入状态确定至少一个参考存储器单元的写入状态，写入至少一个存储单元，以及将至少一个参考存储器单元写入给定写入 州。

    Memory device and method for verifying information stored in memory cells
    8.
    发明授权
    Memory device and method for verifying information stored in memory cells 有权
    用于验证存储在存储单元中的信息的存储器件和方法

    公开(公告)号：US07457144B2

    公开(公告)日：2008-11-25

    申请号：US11489702

    申请日：2006-07-19

    申请人： Andreas Kux ,  Detlev Richter

    发明人： Andreas Kux ,  Detlev Richter

    IPC分类号： G11C17/00

    CPC分类号： G11C16/344 ,  G11C16/3445

    摘要： A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.

    摘要翻译： 一种存储器件包括被排列成阵列的多个第一和第二非易失性存储器单元。 每个存储单元存储信息。 存储器件还包括耦合到阵列的存取单元。 访问单元将信息存储在多个第一和第二非易失性存储单元中。 存储器件还包括耦合到阵列的验证单元。 验证单元通过仅验证组的子集来验证存储在第一和第二存储器单元的组中的信息。 该子集包括第二存储器单元中的至少一个。

    Method for testing a memory device, test unit for testing a memory device and memory device
    9.
    发明申请
    Method for testing a memory device, test unit for testing a memory device and memory device 审中-公开
    用于测试存储器件的方法，用于测试存储器件和存储器件的测试单元

    公开(公告)号：US20070025167A1

    公开(公告)日：2007-02-01

    申请号：US11191146

    申请日：2005-07-27

    申请人： Marco Ziegelmayer ,  Detlev Richter ,  Andreas Kux ,  Mirko Reissmann

    发明人： Marco Ziegelmayer ,  Detlev Richter ,  Andreas Kux ,  Mirko Reissmann

    IPC分类号： G11C29/00

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C29/50004

    摘要： A method, a memory device and a test unit to test such memory device is provided. The memory device comprises a memory cell array including a multitude of memory cells each having a variable characteristic. The method comprises identifying the characteristic of each memory cell and assigning memory cells of the multitude of memory cells to a weak group in dependence on the identified characteristic. Then the stored information of the memory cells assigned to the weak group is restored in order to modify the characteristics of these memory cells.

    摘要翻译： 提供了一种测试这种存储器件的方法，存储器件和测试单元。 存储器件包括存储单元阵列，其包括多个具有可变特性的存储单元。 该方法包括根据所识别的特征来识别每个存储器单元的特性并将多个存储器单元的存储单元分配给弱组。 然后恢复分配给弱组的存储单元的存储信息，以便修改这些存储单元的特性。

    Memory device and method providing logic connections for data transfer
    10.
    发明授权
    Memory device and method providing logic connections for data transfer 有权
    提供用于数据传输的逻辑连接的存储器件和方法

    公开(公告)号：US07940575B2

    公开(公告)日：2011-05-10

    申请号：US12058191

    申请日：2008-03-28

    申请人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

    发明人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C16/06

    CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

    摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

    摘要翻译： 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。