公开(公告)号：US08263495B2

公开(公告)日：2012-09-11

申请号：US12642745

申请日：2009-12-18

Applicant: Ting-Yi Lin ,  Chi-Yuan Wen ,  Chuang Tse Chuan ,  Miau-Shing Tsay ,  Ming Li Wu

Inventor： Ting-Yi Lin ,  Chi-Yuan Wen ,  Chuang Tse Chuan ,  Miau-Shing Tsay ,  Ming Li Wu

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76802 ,  H01L21/31116 ,  H01L21/76807

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract translation: 在晶片上形成集成电路结构的方法包括提供包括第一静电卡盘（ESC）的第一蚀刻器; 将晶片放置在第一ESC上; 以及使用所述第一蚀刻器在所述晶片中形成通孔。 在形成通孔开口的步骤之后，将第一反向去卡盘电压施加到第一ESC以释放晶片。 该方法还包括将晶片放置在第二蚀刻器的第二ESC上; 并且使用第二蚀刻器执行蚀刻步骤以在晶片中形成附加的开口。 在形成附加开口的步骤之后，向第二ESC施加第二反向去卡盘电压以释放晶片。 第二反向去卡盘电压与第一反向去卡盘电压不同。

公开(公告)号：US20110147338A1

公开(公告)日：2011-06-23

申请号：US12642747

申请日：2009-12-18

Applicant: Ting-Yi Lin ,  Chi-Yuan Wen

Inventor： Ting-Yi Lin ,  Chi-Yuan Wen

IPC: H05K3/00

CPC classification number: H01L21/31138 ,  H01L21/31116 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/76814

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract translation: 在晶片上形成集成电路结构的方法包括提供具有静电卡盘（ESC）的蚀刻器; 并将晶片放置在ESC上。 晶片在导电特征上包括导电特征和介电层。 该方法还包括在晶片上形成和图案化光致抗蚀剂; 并使用蚀刻器蚀刻电介质层以在晶片中形成通孔。 对光致抗蚀剂进行灰化以除去光致抗蚀剂。 对晶片进行氧中和。 执行脱卡步骤以从ESC释放晶片。

公开(公告)号：US09660329B2

公开(公告)日：2017-05-23

申请号：US14048042

申请日：2013-10-08

Applicant: Ting-Yi Lin ,  Tsung-Hsun Hsieh ,  Chi-Hsien Chiu ,  Yu-Chia Chang

Inventor： Ting-Yi Lin ,  Tsung-Hsun Hsieh ,  Chi-Hsien Chiu ,  Yu-Chia Chang

IPC: H01Q11/00 ,  H01Q1/36 ,  H01Q1/24 ,  H01Q9/16

CPC classification number: H01Q1/36 ,  H01Q1/243 ,  H01Q9/16

Abstract: A directional antenna including a ground plane, a feeding element and a radiating element is provided. The feeding element is adjacent to the ground plane and includes a feeding point. A coupling gap is formed between the radiating element and the feeding element, and the radiating element includes a coupling point. Both the coupling point of the radiating element and the feeding point of the feeding element are at the perpendicular line of a ground plane. Further, a distance between the coupling point and an open end of the radiating element is smaller than 0.16λ of a resonant frequency of the directional antenna.

公开(公告)号：US08293649B2

公开(公告)日：2012-10-23

申请号：US12642747

申请日：2009-12-18

Applicant: Ting-Yi Lin ,  Chi-Yuan Wen

Inventor： Ting-Yi Lin ,  Chi-Yuan Wen

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31138 ,  H01L21/31116 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/76814

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract translation: 在晶片上形成集成电路结构的方法包括提供具有静电卡盘（ESC）的蚀刻器; 并将晶片放置在ESC上。 晶片在导电特征上包括导电特征和介电层。 该方法还包括在晶片上形成和图案化光致抗蚀剂; 并使用蚀刻器蚀刻电介质层以在晶片中形成通孔。 对光致抗蚀剂进行灰化以除去光致抗蚀剂。 对晶片进行氧中和。 执行脱卡步骤以从ESC释放晶片。

公开(公告)号：US20090250816A1

公开(公告)日：2009-10-08

申请号：US12115300

申请日：2008-05-05

Applicant: Tsung Shune CHIN ,  Ting Yi Lin ,  Huai Yu Cheng ,  Jau Shiung Fang ,  Chin Fu Chiu

Inventor： Tsung Shune CHIN ,  Ting Yi Lin ,  Huai Yu Cheng ,  Jau Shiung Fang ,  Chin Fu Chiu

IPC: H01L23/52

CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76846

Abstract: Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the thickness of diffusion barrier layer must be thinner than 10 nm. For example, a thickness of 2 nm will be called for at the feature size 27 nm. Disclosed in the present invention is ultra-thin barrier materials and structures based on tantalum silicon carbide, and its composite with another metallic layer Ru film. The retarding temperature, by which no evidence of copper diffusion can be identified, is 600˜850° C. depending on thickness, composition and film structure, at a thickness 1.6˜5 nm.

Abstract translation: 在IC加工中的铜金属化期间需要扩散阻挡层，以防止Cu扩散到接触硅材料中并且反应形成硅化铜，其消耗Cu并劣化导电性。 随着诸如那些小于90纳米（nm）的IC器件的特征尺寸的减小，扩散阻挡层的厚度必须比10nm薄。 例如，在特征尺寸27nm处将要求2nm的厚度。 在本发明中公开了基于钽碳化硅的超薄阻挡材料和结构，并且其与另一种金属层Ru膜的复合物。 取决于厚度，组成和膜结构，厚度为1.6〜5nm，延伸温度根据其中没有铜扩散的迹象可以确定为600〜850℃。

公开(公告)号：US20140111399A1

公开(公告)日：2014-04-24

申请号：US14048042

申请日：2013-10-08

Applicant: Ting-Yi Lin ,  Tsung-Hsun Hsieh ,  Chi-Hsien Chiu ,  Yu-Chia Chang

Inventor： Ting-Yi Lin ,  Tsung-Hsun Hsieh ,  Chi-Hsien Chiu ,  Yu-Chia Chang

IPC: H01Q1/36

CPC classification number: H01Q1/36 ,  H01Q1/243 ,  H01Q9/16

Abstract: A directional antenna including a ground plane, a feeding element and a radiating element is provided. The feeding element is adjacent to the ground plane and includes a feeding point. A coupling gap is formed between the radiating element and the feeding element, and the radiating element includes a coupling point. Both the coupling point of the radiating element and the feeding point of the feeding element are at the perpendicular line of a ground plane. Further, a distance between the coupling point and an open end of the radiating element is smaller than 0.16λ of a resonant frequency of the directional antenna.

Abstract translation: 提供了包括接地平面，馈电元件和辐射元件的定向天线。 馈电元件与接地平面相邻并且包括馈电点。 在辐射元件和馈电元件之间形成耦合间隙，并且辐射元件包括耦合点。 辐射元件的耦合点和馈电元件的馈电点都在接地平面的垂直线处。 此外，耦合点和辐射元件的开路端之间的距离小于定向天线的谐振频率的0.16λ。

公开(公告)号：US20110151669A1

公开(公告)日：2011-06-23

申请号：US12642745

申请日：2009-12-18

Applicant: Ting-Yi Lin ,  Chi-Yuan Wen ,  Chuang Tse Chuan ,  Miau-Shing Tsay ,  Ming Li Wu

Inventor： Ting-Yi Lin ,  Chi-Yuan Wen ,  Chuang Tse Chuan ,  Miau-Shing Tsay ,  Ming Li Wu

IPC: H01L21/461

CPC classification number: H01L21/76802 ,  H01L21/31116 ,  H01L21/76807

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract translation: 在晶片上形成集成电路结构的方法包括提供包括第一静电卡盘（ESC）的第一蚀刻器; 将晶片放置在第一ESC上; 以及使用所述第一蚀刻器在所述晶片中形成通孔。 在形成通孔开口的步骤之后，将第一反向去卡盘电压施加到第一ESC以释放晶片。 该方法还包括将晶片放置在第二蚀刻器的第二ESC上; 并且使用第二蚀刻器执行蚀刻步骤以在晶片中形成附加的开口。 在形成附加开口的步骤之后，向第二ESC施加第二反向去卡盘电压以释放晶片。 第二反向去卡盘电压与第一反向去卡盘电压不同。