公开(公告)号：US20060215436A1

公开(公告)日：2006-09-28

申请号：US11442902

申请日：2006-05-30

申请人： Seong-ho Jeung ,  Young-Keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-Keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

公开(公告)号：US20050018465A1

公开(公告)日：2005-01-27

申请号：US10869386

申请日：2004-06-16

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/14 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

摘要翻译： 金属（或通过）可编程ROM的存储单元结构，由此在可编程ROM的位单元之间共享晶体管。 这样的存储单元结构可以包括：字线; 有点线 第一和第二虚拟接地线; 接地线 由字线和第一虚拟接地线的信号选择的第一位单元; 以及由字线和第二虚拟接地线的信号选择的第二位单元，其中单元晶体管的一侧连接到位线由第一和第二位单元共享。 此外，单元晶体管的另一侧可以浮置或连接到位线，或者替代地，连接到第一虚拟接地线，第二虚拟接地线和接地线中的任一个，以及单元晶体管的栅极 连接到字线。

公开(公告)号：US07382640B2

公开(公告)日：2008-06-03

申请号：US11032362

申请日：2005-01-10

申请人： Joong-Eon Lee ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Joong-Eon Lee ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A high-speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided. The programmable ROM system has a plurality of memory cell, each of which has a gate, a first electrode, and a second electrode; a plurality of word lines, each of which is connected to the gates of a predetermined number of cells of the plurality of memory cells; a plurality of bit lines, each of which is connected to the first electrodes of a predetermined number of memory cells of the plurality of memory cells and is arranged in a direction substantially perpendicular to the word lines; and a plurality of virtual ground lines, each of which is selectively connected to ground in response to control signals, and is arranged in a direction actually perpendicular to the word lines, wherein the plurality of memory cells are programmed to predetermined logic levels by selectively connecting the second electrode of each of the plurality of memory cells to the plurality of virtual ground lines. The high-speed programmable ROM system selectively connects the source of a cell transistor to a virtual ground line according to ROM data such that the capacitance of a bit line can be maintained at a predetermined level without becoming excessively great or small. Thus, the operation speed of the programmable ROM increases and misreading programmed data is minimized.

摘要翻译： 提供了一种高速可编程ROM，其存储单元结构以及用于从可编程ROM写入/读取数据的方法。 可编程ROM系统具有多个存储单元，每个存储单元具有栅极，第一电极和第二电极; 多个字线，其各自连接到所述多个存储单元中的预定数量的单元的栅极; 多个位线，其各自连接到多个存储单元中的预定数量的存储单元的第一电极，并且布置在基本上垂直于字线的方向上; 以及多个虚拟接地线，每个虚拟接地线响应于控制信号被选择性地连接到地，并且被布置在与字线实际垂直的方向上，其中通过选择性地连接来将多个存储器单元编程到预定的逻辑电平 所述多个存储单元中的每一个的第二电极连接到所述多个虚拟接地线。 高速可编程ROM系统根据ROM数据选择性地将单元晶体管的源极连接到虚拟接地线，使得位线的电容可以保持在预定的水平而不会变得过大或较小。 因此，可编程ROM的操作速度增加并且程序数据的误读最小化​​。

公开(公告)号：US20050122760A1

公开(公告)日：2005-06-09

申请号：US11032362

申请日：2005-01-10

申请人： Joong-Eon Lee ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Joong-Eon Lee ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/18 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C17/126

摘要： A high-speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided. The programmable ROM system has a plurality of memory cell, each of which has a gate, a first electrode, and a second electrode; a plurality of word lines, each of which is connected to the gates of a predetermined number of cells of the plurality of memory cells; a plurality of bit lines, each of which is connected to the first electrodes of a predetermined number of memory cells of the plurality of memory cells and is arranged in a direction substantially perpendicular to the word lines; and a plurality of virtual ground lines, each of which is selectively connected to ground in response to control signals, and is arranged in a direction actually perpendicular to the word lines, wherein the plurality of memory cells are programmed to predetermined logic levels by selectively connecting the second electrode of each of the plurality of memory cells to the plurality of virtual ground lines. The high-speed programmable ROM system selectively connects the source of a cell transistor to a virtual ground line according to ROM data such that the capacitance of a bit line can be maintained at a predetermined level without becoming excessively great or small. Thus, the operation speed of the programmable ROM increases and misreading programmed data is minimized.

摘要翻译： 提供了一种高速可编程ROM，其存储单元结构以及用于从可编程ROM写入/读取数据的方法。 可编程ROM系统具有多个存储单元，每个存储单元具有栅极，第一电极和第二电极; 多个字线，其各自连接到所述多个存储单元中的预定数量的单元的栅极; 多个位线，其各自连接到多个存储单元中的预定数量的存储单元的第一电极，并且布置在基本上垂直于字线的方向上; 以及多个虚拟接地线，每个虚拟接地线响应于控制信号被选择性地连接到地，并且被布置在与字线实际垂直的方向上，其中通过选择性地连接来将多个存储器单元编程到预定的逻辑电平 所述多个存储单元中的每一个的第二电极连接到所述多个虚拟接地线。 高速可编程ROM系统根据ROM数据选择性地将单元晶体管的源极连接到虚拟接地线，使得位线的电容可以保持在预定的水平而不会变得过大或较小。 因此，可编程ROM的操作速度增加并且程序数据的误读最小化​​。

公开(公告)号：US07075809B2

公开(公告)日：2006-07-11

申请号：US10869386

申请日：2004-06-16

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

公开(公告)号：US06975528B2

公开(公告)日：2005-12-13

申请号：US10756962

申请日：2004-01-13

申请人： Young-Sook Do

发明人： Young-Sook Do

IPC分类号： G11C17/18 ,  G11C7/00 ,  G11C7/14 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/08 ,  G11C17/12

CPC分类号： G11C7/14 ,  G11C16/28 ,  G11C17/126

摘要： The present invention relates to an improved read only memory device. The read only memory device includes a read only memory cell array with a plurality of first read only memory cells and a plurality of second read only memory cells. A reference memory cell array includes a plurality of first reference memory cells and at least one second reference memory cell. A dummy memory cell array includes a plurality of first dummy memory cells and a plurality of second dummy memory cells. A reference word line selecting circuit selects the reference word line responsive to a row address.

摘要翻译： 本发明涉及一种改进的只读存储器件。 只读存储器件包括具有多个第一只读存储器单元和多个第二只读存储器单元的只读存储器单元阵列。 参考存储单元阵列包括多个第一参考存储单元和至少一个第二参考存储单元。 虚拟存储单元阵列包括多个第一虚拟存储单元和多个第二虚拟存储单元。 参考字线选择电路响应于行地址选择参考字线。

公开(公告)号：US07480166B2

公开(公告)日：2009-01-20

申请号：US11442902

申请日：2006-05-30

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

公开(公告)号：US06861714B2

公开(公告)日：2005-03-01

申请号：US10124717

申请日：2002-04-17

申请人： Joong-Eon Lee ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Joong-Eon Lee ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/18 ,  G11C17/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： G11C17/126

摘要： A high speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided. The programmable ROM system has a plurality of memory cell, each of which has a gate, a first electrode, and a second electrode; a plurality of word lines, each of which is connected to the gates of a predetermined number of cells of the plurality of memory cells; a plurality of bit lines, each of which is connected to the first electrodes of a predetermined number of memory cells of the plurality of memory cells and is arranged in a direction substantially perpendicular to the word lines; and a plurality of virtual ground lines, each of which is selectively connected to ground in response to control signals, and is arranged in a direction actually perpendicular to the word lines, wherein the plurality of memory cells are programmed to predetermined logic levels by selectively connecting the second electrode of each of the plurality of memory cells to the plurality of virtual ground lines. The high speed programmable ROM system selectively connects the source of a cell transistor to a virtual ground line according to ROM data such that the capacitance of a bit line can be maintained at a predetermined level without becoming excessively great or small. Thus, the operation speed of the programmable ROM increases and misreading programmed data is minimized.

摘要翻译： 提供了一种高速可编程ROM，其存储单元结构以及用于从可编程ROM写入/读取数据的方法。 可编程ROM系统具有多个存储单元，每个存储单元具有栅极，第一电极和第二电极; 多个字线，其各自连接到所述多个存储单元中的预定数量的单元的栅极; 多个位线，其各自连接到多个存储单元中的预定数量的存储单元的第一电极，并且布置在基本上垂直于字线的方向上; 以及多个虚拟接地线，每个虚拟接地线响应于控制信号被选择性地连接到地，并且被布置在与字线实际垂直的方向上，其中通过选择性地连接来将多个存储器单元编程到预定的逻辑电平 所述多个存储单元中的每一个的第二电极连接到所述多个虚拟接地线。 高速可编程ROM系统根据ROM数据选择性地将单元晶体管的源极连接到虚拟接地线，使得位线的电容可以保持在预定的水平而不会变得过大或较小。 因此，可编程ROM的操作速度增加并且程序数据的误读最小化​​。

公开(公告)号：US06771528B2

公开(公告)日：2004-08-03

申请号：US10085367

申请日：2002-02-28

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C700

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

摘要翻译： 金属（或通过）可编程ROM的存储单元结构，由此在可编程ROM的位单元之间共享晶体管。 这样的存储单元结构可以包括：字线; 有点线 第一和第二虚拟接地线; 接地线 由字线和第一虚拟接地线的信号选择的第一位单元; 以及由字线和第二虚拟接地线的信号选择的第二位单元，其中单元晶体管的一侧连接到位线由第一和第二位单元共享。 此外，单元晶体管的另一侧可以浮置或连接到位线，或者替代地，连接到第一虚拟接地线，第二虚拟接地线和接地线中的任一个，以及单元晶体管的栅极 连接到字线。