公开(公告)号：US20150146794A1

公开(公告)日：2015-05-28

申请号：US14092524

申请日：2013-11-27

申请人： Zenverge, Inc.

发明人： Dzung Hoang

IPC分类号： H04N19/40 ,  H04N19/96 ,  H04N19/70 ,  H04N19/91

CPC分类号： H04N19/40 ,  H04N19/129 ,  H04N19/13 ,  H04N19/88 ,  H04N19/91 ,  H04N19/96 ,  H04N21/234309

摘要： A two-stage context adaptive binary arithmetic coding (CABAC) parser is provided to efficiently transcode an input video bitstream that is partitioned into tiles into a non-tiled based video bitstream. A picture of the input video bitstream is partitioned into one or more tiles, each of which has multiple coding tree units (CTUs) according to the HEVC standard. The two-stage CABAC parser parses the input video bitstream in tile scan order in the first stage and generates a list of identified CTUs, whose CABAC state data are saved for the second stage parsing. In the second stage parsing, the two-stage parser parses the same input video bitstream in raster scan order using the saved CABAC state data of the identified CTUs.

摘要翻译： 提供两阶段上下文自适应二进制算术编码（CABAC）解析器以将分割成瓦片的输入视频比特流有效地转码成非基于平铺的视频比特流。 将输入视频比特流的图像划分为一个或多个瓦片，每个瓦片根据HEVC标准具有多个编码树单元（CTU）。 两级CABAC解析器在第一阶段以瓦片扫描顺序解析输入视频比特流，并生成识别的CTU的列表，其CABAC状态数据被保存用于第二阶段解析。 在第二阶段解析中，两级解析器使用所识别的CTU的保存的CABAC状态数据以光栅扫描顺序解析相同的输入视频比特流。

公开(公告)号：US09053752B1

公开(公告)日：2015-06-09

申请号：US14188642

申请日：2014-02-24

申请人： Zenverge, Inc.

发明人： Anthony D. Masterson

IPC分类号： G09G5/00 ,  G11B27/30 ,  H04N21/4402 ,  G06T9/00 ,  G09G5/393 ,  G06T11/60 ,  H04N19/00 ,  G09G5/14 ,  H04N21/426 ,  H04N21/44 ,  G06T19/00 ,  G06T1/20 ,  G06T11/00

CPC分类号： G09G5/14 ,  G06T1/20 ,  G06T9/00 ,  G06T11/00 ,  G06T11/60 ,  G06T19/00 ,  G09G5/393 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/125 ,  G11B27/30 ,  H04N19/00 ,  H04N19/27 ,  H04N19/29 ,  H04N21/42653 ,  H04N21/44 ,  H04N21/440218 ,  H04N21/440263

摘要： Systems and methods for layering a graphics plane on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A graphics plane is received from a graphics processing path, wherein the graphics plane comprises a set of graphics macroblocks. The graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.

摘要翻译： 本文公开了用于在压缩视频信号之上分层图形平面的系统和方法。 从视频处理路径接收经处理的视频流，其中所处理的视频流包括视频宏块流。 从图形处理路径接收图形平面，其中图形平面包括一组图形宏块。 图形平面被分层在被处理的视频流之上以产生输出视频流。 分层包括将来自视频宏块的视频宏块与来自该组图形宏块的图形宏块混合。 通过在时间分层一个宏块，当接收到压缩输入流时，图形叠加可以实时地或比实时更快地发生。

公开(公告)号：US20130195191A1

公开(公告)日：2013-08-01

申请号：US13782925

申请日：2013-03-01

申请人： Zenverge, Inc.

发明人： Jacob Rojit ,  Alexander Naum Kipnis ,  Behzad R. Sayyah

IPC分类号： H04N7/26

CPC分类号： H04N19/00733 ,  H04N19/433 ,  H04N19/51

摘要： A system (and a method) are disclosed for intelligently fetch one or multiple reference blocks from memory for each block to be motion compensated or motion estimated within a video processing system. The system includes a reference block configuration evaluation unit and a motion compensation memory fetching unit. The reference block configuration evaluation unit analyzes the reference block configuration of the block being motion compensated with a plurality of reference block configurations of its neighboring blocks. In response to a reference block configuration evaluation result, the reference block configuration evaluation unit decides the configuration of reference blocks to be fetched from a memory. The motion vector memory fetching unit fetches the number of reference blocks for motion compensation accordingly.

摘要翻译： 公开了一种系统（和方法），用于从视频处理系统内的运动补偿或运动估计的每个块智能地取出一个或多个参考块。 该系统包括参考块配置评估单元和运动补偿存储器提取单元。 参考块配置评估单元利用其相邻块的多个参考块配置来分析被运动补偿的块的参考块配置。 参考块配置评估单元响应于参考块配置评估结果来决定要从存储器取出的参考块的配置。 运动矢量存储器取出单元相应地获取用于运动补偿的参考块的数量。

公开(公告)号：US20150163540A1

公开(公告)日：2015-06-11

申请号：US14099547

申请日：2013-12-06

申请人： Zenverge, Inc.

发明人： Anthony D. Masterson

IPC分类号： H04N21/4363 ,  H04N21/426 ,  H04N21/61 ,  H04N21/438 ,  H04N21/4408 ,  H04N21/4402

CPC分类号： H04N21/4382 ,  H04N21/43853 ,  H04N21/6125 ,  H04N21/64322 ,  H04N21/64784

摘要： A content delivery gateway receives a video sequence transmitted over an Internet Protocol network and the video sequence is destined to multiple digital display devices. The content delivery gateway transcodes the video sequence into one of multiple video formats, e.g., high efficiency video coding (HEVC) format to advanced video coding (AVC) format, HEVC OR AVC to MPEG-2 format. The content delivery gateway generates an IP-based user interface including video overly that allows existing quadrature amplitude modulation (QAM) based set-top boxes and digital TV adapters to receive features associated with IP video technology. The content delivery gateway further adds content protection by transcripting the video sequence. By deploying IP to QAM bridges, the content delivery gateway serves increasingly large numbers of IP-based digital display devices including tablets and smartphones while continuing to support existing QAM-based display devices.

摘要翻译： 内容发送网关接收通过因特网协议网络发送的视频序列，视频序列指定给多个数字显示装置。 内容传送网关将视频序列转换为多种视频格式之一，例如高效视频编码（HEVC）格式到高级视频编码（AVC）格式，HEVC或AVC至MPEG-2格式。 内容传送网关生成包括视频的基于IP的用户界面，其允许现有的基于正交幅度调制（QAM）的机顶盒和数字电视适配器接收与IP视频技术相关联的特征。 内容传送网关通过转录视频序列进一步增加内容保护。 通过将IP部署到QAM网桥，内容传送网关将在不断支持现有的基于QAM的显示设备的同时，增加大量基于IP的数字显示设备，包括平板电脑和智能手机。

公开(公告)号：US20130202028A1

公开(公告)日：2013-08-08

申请号：US13835158

申请日：2013-03-15

申请人： Zenverge, Inc.

发明人： Jun Xin ,  Behzad R. Sayyah ,  William Ka-ming Chan

IPC分类号： H04N7/26

CPC分类号： H04N19/40 ,  H04N19/15 ,  H04N19/423 ,  H04N19/44 ,  H04N19/70

摘要： A system (and a method) are disclosed for a video processing system with enhanced entropy coding performance. The system includes an entropy decoder configured to divide decoding of an input video stream into arithmetic decoding and syntax decoding. The entropy decoder includes an arithmetic decoding module, a syntax decoding module, a memory management module and a memory buffer connecting the two decoding modules. The arithmetic decoding module is configured to decode the input video stream into multiple bins of decoded input video stream and the syntax decoding module is configured to decode the bins of arithmetically decoded input videos stream into one or more syntax elements. The memory management module uses the memory buffer to accelerate the coding performances of arithmetic decoding and syntax decoding. The system also includes a corresponding entropy encoder configured to encode a video stream with improved coding performance.

摘要翻译： 公开了一种具有增强的熵编码性能的视频处理系统的系统（和方法）。 该系统包括熵解码器，其被配置为将输入视频流的解码划分为算术解码和语法解码。 熵解码器包括算术解码模块，语法解码模块，存储器管理模块和连接两个解码模块的存储缓冲器。 算术解码模块被配置为将输入视频流解码成解码的输入视频流的多个分组，并且语法解码模块被配置为将算术解码的输入视频流的分组解码为一个或多个语法元素。 存储器管理模块使用存储器缓冲器来加速算术解码和语法解码的编码性能。 该系统还包括对应的熵编码器，其被配置为对具有改进的编码性能的视频流进行编码。